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DaDianNao: A Machine-Learning Supercomputer
DaDianNao: A Machine-Learning Supercomputer
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Ata de Congresso 		Adicionar ao Meu Espaço

DaDianNao: A Machine-Learning Supercomputer

Chen, Yunji ; Luo, Tao ; Liu, Shaoli ; Zhang, Shijin ; He, Liqiang ; Wang, Jia ; Li, Ling ; Chen, Tianshi ; Xu, Zhiwei ; Sun, Ninghui ; Temam, Olivier

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.609-622

Washington, DC, USA: IEEE Computer Society

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Pipelining a triggered processing element
Pipelining a triggered processing element
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Pipelining a triggered processing element

Repetti, Thomas J. ; Cerqueira, João P. ; Kim, Martha A. ; Seok, Mingoo

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.96-108

New York, NY, USA: ACM

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3
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
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DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator

Zhang, Xiaofan ; Ye, Hanchen ; Wang, Junsong ; Lin, Yonghua ; Xiong, Jinjun ; Hwu, Wen-Mei ; Chen, Deming

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

Association on Computer Machinery

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4
A scalable processing-in-memory accelerator for parallel graph processing
A scalable processing-in-memory accelerator for parallel graph processing
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A scalable processing-in-memory accelerator for parallel graph processing

Ahn, Junwhan ; Hong, Sungpack ; Yoo, Sungjoo ; Mutlu, Onur ; Choi, Kiyoung

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015, p.105-117

New York, NY, USA: ACM

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5
DRISA: a DRAM-based Reconfigurable In-Situ Accelerator
DRISA: a DRAM-based Reconfigurable In-Situ Accelerator
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DRISA: a DRAM-based Reconfigurable In-Situ Accelerator

Li, Shuangchen ; Niu, Dimin ; Malladi, Krishna T. ; Zheng, Hongzhong ; Brennan, Bob ; Xie, Yuan

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.288-301

New York, NY, USA: ACM

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6
Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs
Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs
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Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs

Fang, Haowen ; Mei, Zaidao ; Shrestha, Amar ; Zhao, Ziyi ; Li, Yilan ; Qiu, Qinru

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

Association on Computer Machinery

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7
Outer-loop vectorization: revisited for short SIMD architectures
Outer-loop vectorization: revisited for short SIMD architectures
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Outer-loop vectorization: revisited for short SIMD architectures

Nuzman, Dorit ; Zaks, Ayal

2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008, p.2-11

New York, NY, USA: ACM

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8
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration
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ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration

Yang, Xiaoxuan ; Yan, Bonan ; Li, Hai ; Chen, Yiran

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

Association on Computer Machinery

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9
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture
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PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture

Ahn, Junwhan ; Yoo, Sungjoo ; Mutlu, Onur ; Choi, Kiyoung

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015, p.336-348

New York, NY, USA: ACM

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10
Computation reuse in DNNs by exploiting input similarity
Computation reuse in DNNs by exploiting input similarity
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Computation reuse in DNNs by exploiting input similarity

Riera Villanueva, Marc ; Arnau Montañés, José María ; González Colás, Antonio María

Institute of Electrical and Electronics Engineers (IEEE) 2018

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