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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover
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DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters
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DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters

Zhao, Zhuoran ; Barijough, Kamyar Mirzazad ; Gerstlauer, Andreas

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2348-2359 [Periódico revisado por pares]

New York: IEEE

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2
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput
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SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Ben-Hur, Rotem ; Ronen, Ronny ; Haj-Ali, Ameer ; Bhattacharjee, Debjyoti ; Eliahu, Adi ; Peled, Natan ; Kvatinsky, Shahar

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2434-2447 [Periódico revisado por pares]

New York: IEEE

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3
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors
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High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors

Wang, Siqi ; Ananthanarayanan, Gayathri ; Zeng, Yifan ; Goel, Neeraj ; Pathania, Anuj ; Mitra, Tulika

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2254-2267 [Periódico revisado por pares]

New York: IEEE

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4
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs
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ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs

Lin, Yibo ; Li, Wuxi ; Gu, Jiaqi ; Ren, Haoxing ; Khailany, Brucek ; Pan, David Z.

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.5083-5096 [Periódico revisado por pares]

New York: IEEE

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5
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
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Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

Liang, Yun ; Lu, Liqiang ; Xiao, Qingcheng ; Yan, Shengen

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-04, Vol.39 (4), p.857-870 [Periódico revisado por pares]

New York: IEEE

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6
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine
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OpenTimer v2: A New Parallel Incremental Timing Analysis Engine

Huang, Tsung-Wei ; Guo, Guannan ; Lin, Chun-Xun ; Wong, Martin D. F.

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-04, Vol.40 (4), p.776-789 [Periódico revisado por pares]

New York: IEEE

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7
Accelerating Static Timing Analysis using CPU-GPU Heterogeneous Parallelism
Accelerating Static Timing Analysis using CPU-GPU Heterogeneous Parallelism
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Accelerating Static Timing Analysis using CPU-GPU Heterogeneous Parallelism

Guo, Zizheng ; Huang, Tsung-Wei ; Lin, Yibo

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

IEEE

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8
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism
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SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

Haaswijk, Winston ; Soeken, Mathias ; Mishchenko, Alan ; De Micheli, Giovanni

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-04, Vol.39 (4), p.871-884 [Periódico revisado por pares]

New York: IEEE

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9
Task-Based Parallel Programming for Gate Sizing
Task-Based Parallel Programming for Gate Sizing
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Task-Based Parallel Programming for Gate Sizing

Mangiras, Dimitrios ; Chinnery, David ; Dimitrakopoulos, Giorgos

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1309-1322 [Periódico revisado por pares]

New York: IEEE

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10
k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting
k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting
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k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting

Ray, Sanchita Saha ; Ghosh, Surajeet

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1-1 [Periódico revisado por pares]

New York: IEEE

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