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Radiation-Hardened Cortex-R4F System-on-Chip Prototype With Total Ionizing Dose Dynamic Compensation in 28-nm FD-SOI
Radiation-Hardened Cortex-R4F System-on-Chip Prototype With Total Ionizing Dose Dynamic Compensation in 28-nm FD-SOI
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Radiation-Hardened Cortex-R4F System-on-Chip Prototype With Total Ionizing Dose Dynamic Compensation in 28-nm FD-SOI

Abouzeid, Fady ; de Boissac, Capucine Lecat-Mathieu ; Malherbe, Victor ; Daveau, Jean-Marc ; Asquini, Anna ; Bertin, Valerie ; De-Paoli, Serge ; Gasiot, Gilles ; Timineri, Calogero ; Autran, Jean-Luc ; Roche, Philippe

IEEE transactions on nuclear science, 2021-05, Vol.68 (5), p.1040-1044 [Periódico revisado por pares]

New York: IEEE

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2
Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions
Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions
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Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Balasubramanian, Padmanabhan ; Mastorakis, Nikos

Electronics (Basel), 2018-12, Vol.7 (12), p.369 [Periódico revisado por pares]

Basel: MDPI AG

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Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
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Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology

YAMADA, Junji ; JIMBO, Ushio ; SHIOYA, Ryota ; GOSHIMA, Masahiro ; SAKAI, Shuichi

IEICE Transactions on Electronics, 2017/03/01, Vol.E100.C(3), pp.232-244 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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4
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications
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New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications

Chen, Jiajia ; Chang, Chip-Hong ; Wang, Yujia ; Zhao, Juan ; Rahardja, Susanto

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-04, Vol.37 (4), p.896-900 [Periódico revisado por pares]

IEEE

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5
High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory
High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory
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High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory

Castaneda, Oscar ; Jacobsson, Sven ; Durisi, Giuseppe ; Goldstein, Tom ; Studer, Christoph

IEEE transactions on circuits and systems. II, Express briefs, 2020-05, Vol.67 (5), p.891-895 [Periódico revisado por pares]

New York: IEEE

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6
Using software simulators to enhance the learning of digital logic design for the information technology students
Using software simulators to enhance the learning of digital logic design for the information technology students
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Using software simulators to enhance the learning of digital logic design for the information technology students

Alsadoon, Abeer ; Prasad, P.W.C. ; Beg, Azam

European journal of engineering education, 2017-09, Vol.42 (5), p.533-546 [Periódico revisado por pares]

Abingdon: Taylor & Francis

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7
Introductory digital design & computer architecture curriculum
Introductory digital design & computer architecture curriculum
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Introductory digital design & computer architecture curriculum

Harris, David Money ; Harris, Sarah

2013 IEEE International Conference on Microelectronic Systems Education (MSE), 2013, p.14-16

IEEE

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Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
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Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication

McLaughlin, W.F. ; Mitra, A. ; Nowick, S.M.

IEEE transactions on very large scale integration (VLSI) systems, 2009-07, Vol.17 (7), p.923-928 [Periódico revisado por pares]

New York: IEEE

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9
A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition
A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition
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A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

Chakraborty, Anirban ; Banerjee, Ayan

Journal of real-time image processing, 2020-10, Vol.17 (5), p.1421-1446 [Periódico revisado por pares]

Berlin/Heidelberg: Springer Berlin Heidelberg

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10
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network
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Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network

Sharma, Rahul ; Shrestha, Rahul ; Sharma, Satinder K.

IEEE transactions on circuits and systems. I, Regular papers, 2023-03, Vol.70 (3), p.1298-1310 [Periódico revisado por pares]

New York: IEEE

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