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1
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems
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Projection-based approaches for model reduction of weakly nonlinear, time-varying systems

Phillips, J.R.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-02, Vol.22 (2), p.171-187 [Periódico revisado por pares]

New York: IEEE

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2
Fault testing for reversible circuits
Fault testing for reversible circuits
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Fault testing for reversible circuits

Patel, K.N. ; Hayes, J.P. ; Markov, I.L.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-08, Vol.23 (8), p.1220-1230 [Periódico revisado por pares]

New York: IEEE

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3
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS
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Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

Doboli, A. ; Vemuri, R.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-11, Vol.22 (11), p.1504-1520 [Periódico revisado por pares]

New York: IEEE

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4
The Elmore delay as a bound for RC trees with generalized input signals
The Elmore delay as a bound for RC trees with generalized input signals
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The Elmore delay as a bound for RC trees with generalized input signals

Gupta, R. ; Tutuianu, B. ; Pileggi, L.T.

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-01, Vol.16 (1), p.95-104 [Periódico revisado por pares]

New York, NY: IEEE

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5
A divide-and-conquer algorithm for 3-D capacitance extraction
A divide-and-conquer algorithm for 3-D capacitance extraction
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A divide-and-conquer algorithm for 3-D capacitance extraction

Shi, W. ; Yu, F.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-08, Vol.23 (8), p.1157-1163 [Periódico revisado por pares]

New York: IEEE

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6
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Temporal logic replication for dynamically reconfigurable FPGA partitioning
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Temporal logic replication for dynamically reconfigurable FPGA partitioning

Wai-Kei Mak ; Young, E.F.Y.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-07, Vol.22 (7), p.952-959 [Periódico revisado por pares]

New York: IEEE

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7
Extraction of two-node bridges from large industrial circuits
Extraction of two-node bridges from large industrial circuits
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Extraction of two-node bridges from large industrial circuits

Zachariah, S.T. ; Chakravarty, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-03, Vol.23 (3), p.433-439 [Periódico revisado por pares]

New York: IEEE

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8
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning
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Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning

Kahng, A.B. ; Xu Xu

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-04, Vol.23 (4), p.464-471 [Periódico revisado por pares]

New York: IEEE

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9
Inverter models of CMOS gates for supply current and delay evaluation
Inverter models of CMOS gates for supply current and delay evaluation
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Inverter models of CMOS gates for supply current and delay evaluation

Nabavi-Lishi, A. ; Rumin, N.C.

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-10, Vol.13 (10), p.1271-1279 [Periódico revisado por pares]

New York, NY: IEEE

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10
Time-domain macromodels for VLSI interconnect analysis
Time-domain macromodels for VLSI interconnect analysis
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Time-domain macromodels for VLSI interconnect analysis

Seok-Yoon Kim ; Gopal, N. ; Pillage, L.T.

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-10, Vol.13 (10), p.1257-1270 [Periódico revisado por pares]

New York, NY: IEEE

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