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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover Nome da Publicação: Ieee Trans. On Computer-Aided Design remover
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Optimal integer delay-budget assignment on directed acyclic graphs
Optimal integer delay-budget assignment on directed acyclic graphs
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Optimal integer delay-budget assignment on directed acyclic graphs

Bozorgzadeh, E. ; Ghiasi, S. ; Takahashi, A. ; Sarrafzadeh, M.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-08, Vol.23 (8), p.1184-1199 [Periódico revisado por pares]

New York: IEEE

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2
A new class of iterative Steiner tree heuristics with good performance
A new class of iterative Steiner tree heuristics with good performance
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A new class of iterative Steiner tree heuristics with good performance

Kahng, A.B. ; Robins, G.

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-07, Vol.11 (7), p.893-902 [Periódico revisado por pares]

NEW YORK: IEEE

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3
Network-flow-based multiway partitioning with area and pin constraints
Network-flow-based multiway partitioning with area and pin constraints
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Network-flow-based multiway partitioning with area and pin constraints

Huiqun Liu ; Wong, D.F.

IEEE transactions on computer-aided design of integrated circuits and systems, 1998-01, Vol.17 (1), p.50-59 [Periódico revisado por pares]

New York, NY: IEEE

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4
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
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A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

Bachtold, M. ; Spasojevic, M. ; Lage, C. ; Ljung, P.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-03, Vol.19 (3), p.325-338 [Periódico revisado por pares]

New York: IEEE

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5
Test set compaction for combinational circuits
Test set compaction for combinational circuits
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Test set compaction for combinational circuits

Chang, Jau-Shien ; Lin, Chen-Shang

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-11, Vol.14 (11), p.1370-1378 [Periódico revisado por pares]

New York, NY: IEEE

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6
Automatic generation of analytical models for interconnect capacitances
Automatic generation of analytical models for interconnect capacitances
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Automatic generation of analytical models for interconnect capacitances

Choudhury, U. ; Sangiovanni-Vincentelli, A.

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-04, Vol.14 (4), p.470-480 [Periódico revisado por pares]

New York, NY: IEEE

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7
Circuit clustering for delay minimization under area and pin constraints
Circuit clustering for delay minimization under area and pin constraints
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Circuit clustering for delay minimization under area and pin constraints

Yang, H.H. ; Wong, D.F.

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-09, Vol.16 (9), p.976-986 [Periódico revisado por pares]

New York, NY: IEEE

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8
Excellerator: custom CMOS leaf cell layout generator
Excellerator: custom CMOS leaf cell layout generator
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Excellerator: custom CMOS leaf cell layout generator

Poirier, C.J.

IEEE transactions on computer-aided design of integrated circuits and systems, 1989-07, Vol.8 (7), p.744-755 [Periódico revisado por pares]

New York, NY: IEEE

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