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Refinado por: Nome da Publicação: Ieee Journal Of Solid-State Circuits remover
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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

Mingu Kang ; Gonugondla, Sujan K. ; Patil, Ameya ; Shanbhag, Naresh R.

IEEE journal of solid-state circuits, 2018-02, Vol.53 (2), p.642-655 [Periódico revisado por pares]

New York: IEEE

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12
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications
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A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Yin, Shouyi ; Ouyang, Peng ; Tang, Shibin ; Tu, Fengbin ; Li, Xiudong ; Zheng, Shixuan ; Lu, Tianyi ; Gu, Jiangyuan ; Liu, Leibo ; Wei, Shaojun

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.968-982 [Periódico revisado por pares]

New York: IEEE

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13
An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS
An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS
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An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

Moons, Bert ; Verhelst, Marian

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.903-914 [Periódico revisado por pares]

New York: IEEE

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14
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS
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STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS

Yuan, Zhe ; Liu, Yongpan ; Yue, Jinshan ; Yang, Yixiong ; Wang, Jingyu ; Feng, Xiaoyu ; Zhao, Jian ; Li, Xueqing ; Yang, Huazhong

IEEE journal of solid-state circuits, 2020-02, Vol.55 (2), p.465-477 [Periódico revisado por pares]

New York: IEEE

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15
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
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A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

Cheng, Cheng-Hsiang ; Tsai, Ping-Yuan ; Yang, Tzu-Yi ; Cheng, Wan-Hsueh ; Yen, Ting-Yang ; Luo, Zhicong ; Qian, Xin-Hong ; Chen, Zhi-Xin ; Lin, Tzu-Han ; Chen, Wei-Hong ; Chen, Wei-Ming ; Liang, Sheng-Fu ; Shaw, Fu-Zen ; Chang, Cheng-Siu ; Hsin, Yue-Loong ; Lee, Chen-Yi ; Ker, Ming-Dou ; Wu, Chung-Yu

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3314-3326 [Periódico revisado por pares]

New York: IEEE

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16
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching
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HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching

Han, Donghyeon ; Im, Dongseok ; Park, Gwangtae ; Kim, Youngwoo ; Song, Seokchan ; Lee, Juhyoung ; Yoo, Hoi-Jun

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2858-2869 [Periódico revisado por pares]

New York: IEEE

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17
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports
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Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

Lin, Zhiting ; Zhu, Zhiyong ; Zhan, Honglan ; Peng, Chunyu ; Wu, Xiulong ; Yao, Yuan ; Niu, Jianchao ; Chen, Junning

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2832-2844 [Periódico revisado por pares]

New York: IEEE

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18
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
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STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions

Yamamoto, Kasho ; Kawamura, Kazushi ; Ando, Kota ; Mertig, Normann ; Takemoto, Takashi ; Yamaoka, Masanao ; Teramoto, Hiroshi ; Sakai, Akira ; Takamaeda-Yamazaki, Shinya ; Motomura, Masato

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.165-178 [Periódico revisado por pares]

New York: IEEE

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19
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
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DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

Whatmough, Paul N. ; Lee, Sae Kyu ; Brooks, David ; Wei, Gu-Yeon

IEEE journal of solid-state circuits, 2018-09, Vol.53 (9), p.2722-2731 [Periódico revisado por pares]

New York: IEEE

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20
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
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SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference

Zhang, Jie-Fang ; Lee, Ching-En ; Liu, Chester ; Shao, Yakun Sophia ; Keckler, Stephen W. ; Zhang, Zhengya

IEEE journal of solid-state circuits, 2021-02, Vol.56 (2), p.636-647 [Periódico revisado por pares]

New York: IEEE

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