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DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNsHanson, Edward ; Li, Shiyu ; Qian, Xuehai ; Li, Hai Helen ; Chen, YiranIEEE transactions on computers, 2023-03, Vol.72 (3), p.880-892 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End DevicesZhang, Chong ; Li, Songfan ; Song, Yihang ; Meng, Qianhe ; Lu, Li ; Zhu, Hongzi ; Wang, XinIEEE transactions on computers, 2024-03, Vol.73 (3), p.747-763 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video CodingHuang, Xiaofeng ; Tang, Ran ; Pan, Rui ; Yin, Haibing ; Wang, Zhao ; Wang, Shiqi ; Ma, SiweiIEEE transactions on circuits and systems for video technology, 2024-07, Vol.34 (7), p.1-1 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded PlatformsLuo, Xiangzhong ; Liu, Di ; Kong, Hao ; Huai, Shuo ; Chen, Hui ; Liu, WeichenIEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1784-1797 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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A Low-Cost Pipelined Architecture Based on a Hybrid Sorting AlgorithmChen, You-Rong ; Ho, Chien-Chia ; Chen, Wei-Ting ; Chen, Pei-YinIEEE transactions on circuits and systems. I, Regular papers, 2024-02, Vol.71 (2), p.1-14 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Zero-Shot Neural Architecture Search: Challenges, Solutions, and OpportunitiesLi, Guihong ; Hoang, Duc ; Bhardwaj, Kartikeya ; Lin, Ming ; Wang, Zhangyang ; Marculescu, RaduIEEE transactions on pattern analysis and machine intelligence, 2024-04, Vol.PP, p.1-19 [Periódico revisado por pares]United States: IEEETexto completo disponível |
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Material Type: Artigo
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An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural NetworksMao, Wei ; Dai, Liuyao ; Li, Kai ; Cheng, Quan ; Wang, Yuhang ; Du, Laimin ; Luo, Shaobo ; Huang, Mingqiang ; Yu, HaoIEEE transactions on very large scale integration (VLSI) systems, 2022-12, Vol.30 (12), p.1-13 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Amdahl's Law in the Multicore EraHill, M.D. ; Marty, M.R.Computer (Long Beach, Calif.), 2008-07, Vol.41 (7), p.33-38 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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Accelerating Sparse DNNs Based on Tiled GEMMGuo, Cong ; Xue, Fengchen ; Leng, Jingwen ; Qiu, Yuxian ; Guan, Yue ; Cui, Weihao ; Chen, Quan ; Guo, MinyiIEEE transactions on computers, 2024-05, Vol.73 (5), p.1275-1289 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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Toward Practical 128-bit General Purpose MicroarchitecturesDeshpande, Chandana S. ; Perais, Arthur ; Petrot, FredericIEEE computer architecture letters, 2023-07, Vol.22 (2), p.1-4 [Periódico revisado por pares]New York: IEEETexto completo disponível |