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Intel virtualization technology
Intel virtualization technology
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Intel virtualization technology

Uhlig, R. ; Neiger, G. ; Rodgers, D. ; Santoni, A.L. ; Martins, F.C.M. ; Anderson, A.V. ; Bennett, S.M. ; Kagi, A. ; Leung, F.H. ; Smith, L.

Computer (Long Beach, Calif.), 2005-05, Vol.38 (5), p.48-56 [Peer Reviewed Journal]

New York, NY: IEEE

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2
The architecture of virtual machines
The architecture of virtual machines
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The architecture of virtual machines

Smith, J.E. ; Ravi Nair

Computer (Long Beach, Calif.), 2005-05, Vol.38 (5), p.32-38 [Peer Reviewed Journal]

New York, NY: IEEE

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3
Pipelined Parallel FFT Architectures via Folding Transformation
Pipelined Parallel FFT Architectures via Folding Transformation
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Pipelined Parallel FFT Architectures via Folding Transformation

Ayinala, M. ; Brown, M. ; Parhi, K. K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1068-1081 [Peer Reviewed Journal]

New York, NY: IEEE

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4
Amdahl's Law in the Multicore Era
Amdahl's Law in the Multicore Era
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Amdahl's Law in the Multicore Era

Hill, M.D. ; Marty, M.R.

Computer (Long Beach, Calif.), 2008-07, Vol.41 (7), p.33-38 [Peer Reviewed Journal]

New York, NY: IEEE

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5
Efficient Hardware Architecture for Sparse Coding
Efficient Hardware Architecture for Sparse Coding
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Efficient Hardware Architecture for Sparse Coding

Kim, Jung Kuk ; Knag, Phil ; Chen, Thomas ; Zhang, Zhengya

IEEE transactions on signal processing, 2014-08, Vol.62 (16), p.4173-4186 [Peer Reviewed Journal]

New York, NY: IEEE

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6
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
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Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

Pham, D.C. ; Aipperspach, T. ; Boerstler, D. ; Bolliger, M. ; Chaudhry, R. ; Cox, D. ; Harvey, P. ; Harvey, P.M. ; Hofstee, H.P. ; Johns, C. ; Kahle, J. ; Kameyama, A. ; Keaty, J. ; Masubuchi, Y. ; Pham, M. ; Pille, J. ; Posluszny, S. ; Riley, M. ; Stasiak, D.L. ; Suzuoki, M. ; Takahashi, O. ; Warnock, J. ; Weitzel, S. ; Wendel, D. ; Yazawa, K.

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.179-196 [Peer Reviewed Journal]

New York, NY: IEEE

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7
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
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Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

Hongyu Liao ; Mandal, M.Kr ; Cockburn, B.F.

IEEE transactions on signal processing, 2004-05, Vol.52 (5), p.1315-1326 [Peer Reviewed Journal]

New York, NY: IEEE

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8
Virtual machine monitors: current technology and future trends
Virtual machine monitors: current technology and future trends
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Virtual machine monitors: current technology and future trends

Rosenblum, M. ; Garfinkel, T.

Computer (Long Beach, Calif.), 2005-05, Vol.38 (5), p.39-47 [Peer Reviewed Journal]

New York, NY: IEEE

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9
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
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Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

CHEN, Tung-Chien ; CHIEN, Shao-Yi ; HUANG, Yu-Wen ; TSAI, Chen-Han ; CHEN, Ching-Yeh ; CHEN, To-Wei ; CHEN, Liang-Gee

IEEE transactions on circuits and systems for video technology, 2006-06, Vol.16 (6), p.673-688 [Peer Reviewed Journal]

New York, NY: IEEE

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10
Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number
Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number
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Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number

CHEN, Tse-Wei ; CHIEN, Shao-Yi

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1336-1345 [Peer Reviewed Journal]

New York, NY: IEEE

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