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Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
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Ata de Congresso 		Adicionar ao Meu Espaço

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture

Shao, Yakun Sophia ; Clemons, Jason ; Venkatesan, Rangharajan ; Zimmer, Brian ; Fojtik, Matthew ; Jiang, Nan ; Keller, Ben ; Klinefelter, Alicia ; Pinckney, Nathaniel ; Raina, Priyanka ; Tell, Stephen G. ; Zhang, Yanqing ; Dally, William J. ; Emer, Joel ; Gray, C. Thomas ; Khailany, Brucek ; Keckler, Stephen W.

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, p.14-27

New York, NY, USA: ACM

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2
Stream-dataflow acceleration
Stream-dataflow acceleration
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Stream-dataflow acceleration

Nowatzki, Tony ; Gangadhar, Vinay ; Ardalani, Newsha ; Sankaralingam, Karthikeyan

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.416-429

ACM

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3
DaDianNao: A Machine-Learning Supercomputer
DaDianNao: A Machine-Learning Supercomputer
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DaDianNao: A Machine-Learning Supercomputer

Chen, Yunji ; Luo, Tao ; Liu, Shaoli ; Zhang, Shijin ; He, Liqiang ; Wang, Jia ; Li, Ling ; Chen, Tianshi ; Xu, Zhiwei ; Sun, Ninghui ; Temam, Olivier

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.609-622

Washington, DC, USA: IEEE Computer Society

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4
SCNN: An accelerator for compressed-sparse convolutional neural networks
SCNN: An accelerator for compressed-sparse convolutional neural networks
Material Type:
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SCNN: An accelerator for compressed-sparse convolutional neural networks

Parashar, Angshuman ; Minsoo Rhu ; Mukkara, Anurag ; Puglielli, Antonio ; Venkatesan, Rangharajan ; Khailany, Brucek ; Emer, Joel ; Keckler, Stephen W. ; Dally, William J.

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.27-40

ACM

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5
OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization
OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization
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OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization

Guo, Cong ; Tang, Jiaming ; Hu, Weiming ; Leng, Jingwen ; Zhang, Chen ; Yang, Fan ; Liu, Yunxin ; Guo, Minyi ; Zhu, Yuhao

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023, p.1-15

New York, NY, USA: ACM

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6
Scheduling techniques for GPU architectures with processing-in-memory capabilities
Scheduling techniques for GPU architectures with processing-in-memory capabilities
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Scheduling techniques for GPU architectures with processing-in-memory capabilities

Pattnaik, Ashutosh ; Xulong Tang ; Adwait Jog ; Kayiran, Onur ; Mishra, Asit K. ; Kandemir, Mahmut T. ; Mutlu, Onur ; Das, Chita R.

2016 International Conference on Parallel Architecture and Compilation Techniques (PACT), 2016, p.31-44

ACM

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7
Architectures of flexible symmetric key crypto enginesaa survey: From hardware coprocessor to multi-crypto-processor system on chip
Architectures of flexible symmetric key crypto enginesaa survey: From hardware coprocessor to multi-crypto-processor system on chip
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Architectures of flexible symmetric key crypto enginesaa survey: From hardware coprocessor to multi-crypto-processor system on chip

Bossuet, Lilian ; Grand, Michael ; Gaspar, Lubos ; Fischer, Viktor ; Gogniat, Guy

ACM computing surveys, 2013-08, Vol.45 (4), p.1-32 [Periódico revisado por pares]

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8
A dynamically configurable coprocessor for convolutional neural networks
A dynamically configurable coprocessor for convolutional neural networks
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A dynamically configurable coprocessor for convolutional neural networks

Chakradhar, Srimat ; Sankaradas, Murugan ; Jakkula, Venkata ; Cadambi, Srihari

Proceedings of the 37th annual international symposium on Computer architecture, 2010, p.247-257

New York, NY, USA: ACM

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9
Exploring Instruction Fusion Opportunities in General Purpose Processors
Exploring Instruction Fusion Opportunities in General Purpose Processors
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Exploring Instruction Fusion Opportunities in General Purpose Processors

Singh, Sawan ; Perais, Arthur ; Jimborean, Alexandra ; Ros, Alberto

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.199-212

Piscataway, NJ, USA: IEEE Press

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10
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks
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Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks

Yang, Tzu-Hsien ; Cheng, Hsiang-Yun ; Yang, Chia-Lin ; Tseng, I-Ching ; Hu, Han-Wen ; Chang, Hung-Sheng ; Li, Hsiang-Pang

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.236-249

New York, NY, USA: ACM

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