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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Periódico revisado por pares]

New York: IEEE

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2
A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices
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A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Tsukada, Mineto ; Kondo, Masaaki ; Matsutani, Hiroki

IEEE transactions on computers, 2020-07, Vol.69 (7), p.1027-1044 [Periódico revisado por pares]

IEEE

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3
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
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An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Wu, Chen ; Deng, Chenchen ; Liu, Leibo ; Han, Jie ; Chen, Jiqiang ; Yin, Shouyi ; Wei, Shaojun

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-08, Vol.34 (8), p.1264-1277 [Periódico revisado por pares]

New York: IEEE

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4
Big Data Driven Edge-Cloud Collaboration Architecture for Cloud Manufacturing: A Software Defined Perspective
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Big Data Driven Edge-Cloud Collaboration Architecture for Cloud Manufacturing: A Software Defined Perspective

Yang, Chen ; Lan, Shulin ; Wang, Lihui ; Shen, Weiming ; Huang, George G. Q.

IEEE access, 2020, Vol.8, p.45938-45950 [Periódico revisado por pares]

Piscataway: IEEE

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5
Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines
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Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines

Shirai, Tatsuhiko ; Togawa, Nozomu

IEEE transactions on computers, 2023-08, Vol.72 (8), p.2151-2164 [Periódico revisado por pares]

IEEE

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6
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins
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How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

Oku, Daisuke ; Tawada, Masashi ; Tanaka, Shu ; Togawa, Nozomu

IEEE transactions on computers, 2022-01, Vol.71 (1), p.223-234 [Periódico revisado por pares]

IEEE

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7
Policy Iteration Approach to the Infinite Horizon Average Optimal Control of Probabilistic Boolean Networks
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Policy Iteration Approach to the Infinite Horizon Average Optimal Control of Probabilistic Boolean Networks

Wu, Yuhu ; Guo, Yuqian ; Toyoda, Mitsuru

IEEE transaction on neural networks and learning systems, 2021-07, Vol.32 (7), p.2910-2924

Piscataway: IEEE

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8
Software-Defined Network Function Virtualization: A Survey
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Software-Defined Network Function Virtualization: A Survey

Li, Yong ; Chen, Min

IEEE access, 2015-01, Vol.3, p.2542-2553 [Periódico revisado por pares]

Piscataway: IEEE

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9
Majority-Inverter Graph: A New Paradigm for Logic Optimization
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Majority-Inverter Graph: A New Paradigm for Logic Optimization

Amaru, Luca ; Gaillardon, Pierre-Emmanuel ; De Micheli, Giovanni

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-05, Vol.35 (5), p.806-819 [Periódico revisado por pares]

New York: IEEE

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10
Open RAN xApps Design and Evaluation: Lessons Learnt and Identified Challenges
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Open RAN xApps Design and Evaluation: Lessons Learnt and Identified Challenges

Hoffmann, Marcin ; Janji, Salim ; Samorzewski, Adam ; Kulacz, Lukasz ; Adamczyk, Cezary ; Dryjanski, Marcin ; Kryszkiewicz, Pawel ; Kliks, Adrian ; Bogucka, Hanna

IEEE journal on selected areas in communications, 2024-02, Vol.42 (2), p.1-1 [Periódico revisado por pares]

New York: IEEE

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