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A methodology and design environment for DSP ASIC fixed point refinement
A methodology and design environment for DSP ASIC fixed point refinement
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A methodology and design environment for DSP ASIC fixed point refinement

Cmar, R. ; Rijnders, L. ; Schaumont, P. ; Vernalde, S. ; Bolsens, I.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.271-276

IEEE

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2
Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family
Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family
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Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family

Fournier, L. ; Arbetman, Y. ; Levinger, M.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.434-441

IEEE

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3
Algorithms for solving Boolean satisfiability in combinational circuits
Algorithms for solving Boolean satisfiability in combinational circuits
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Algorithms for solving Boolean satisfiability in combinational circuits

Guerra e Silva, L. ; Silveira, L.M. ; Marques-Silva, J.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.526-530

IEEE

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4
Symbolic functional vector generation for VHDL specifications
Symbolic functional vector generation for VHDL specifications
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Symbolic functional vector generation for VHDL specifications

Ferrandi, F. ; Fummi, F. ; Gerli, L. ; Sciuto, D.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.442-446

IEEE

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5
A new parameterizable power macro-model for datapath components
A new parameterizable power macro-model for datapath components
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A new parameterizable power macro-model for datapath components

Jochens, G. ; Kruse, L. ; Schmidt, E. ; Nebel, W.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.29-36

IEEE

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6
Wavefront technology mapping
Wavefront technology mapping
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Wavefront technology mapping

Stok, L. ; Iyer, M.A. ; Sullivan, A.J.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.531-536

IEEE

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7
Specification and validation of distributed IP-based designs with JavaCAD
Specification and validation of distributed IP-based designs with JavaCAD
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Specification and validation of distributed IP-based designs with JavaCAD

Dalpasso, M. ; Bogliolo, A. ; Benini, L.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.684-688

IEEE

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8
Fast hardware-software co-simulation using VHDL models
Fast hardware-software co-simulation using VHDL models
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Fast hardware-software co-simulation using VHDL models

Tabbara, B. ; Sgroi, M. ; Sangiovanni-Vincentelli, A. ; Filippi, E. ; Lavagno, L.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.309-316

IEEE

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9
Interval diagram techniques for symbolic model checking of Petri nets
Interval diagram techniques for symbolic model checking of Petri nets
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Interval diagram techniques for symbolic model checking of Petri nets

Strehl, K. ; Thiele, L.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.756-757

IEEE

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10
A method to diagnose faults in linear analog circuits using an adaptive tester
A method to diagnose faults in linear analog circuits using an adaptive tester
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A method to diagnose faults in linear analog circuits using an adaptive tester

Cota, E.F. ; Carro, L. ; Lubaszewski, M.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.184-188

IEEE

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