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A compositional model for the functional verification of high-level synthesis results
A compositional model for the functional verification of high-level synthesis results
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A compositional model for the functional verification of high-level synthesis results

Borrione, D. ; Dushina, J. ; Pierre, L.

IEEE transactions on very large scale integration (VLSI) systems, 2000-10, Vol.8 (5), p.526-530 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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2
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
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A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study

Borrione, D. ; Helmy, A. ; Pierre, L. ; Schmaltz, J.

First International Symposium on Networks-on-Chip (NOCS'07), 2007, p.127-136

IEEE

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3
High-level symbolic simulation for automatic model extraction
High-level symbolic simulation for automatic model extraction
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High-level symbolic simulation for automatic model extraction

Ouchet, F. ; Borrione, D. ; Morin-Allory, K. ; Pierre, L.

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2009, p.218-221

IEEE

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4
Asynchronous Assertion Monitors for multi-Clock Domain System Verification
Asynchronous Assertion Monitors for multi-Clock Domain System Verification
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Asynchronous Assertion Monitors for multi-Clock Domain System Verification

Morin-Allory, K. ; Fesquet, L. ; Borrione, D.

Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), 2006, p.98-102

IEEE

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5
Formal verification of VHDL descriptions in the Prevail environment
Formal verification of VHDL descriptions in the Prevail environment
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Formal verification of VHDL descriptions in the Prevail environment

Borrione, D.D. ; Pierre, L.V. ; Salem, A.M.

IEEE design & test of computers, 1992-06, Vol.9 (2), p.42-56

LOS ALAMITOS: IEEE Computer Society

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6
Formalization of finite state machines with data path for the verification of high-level synthesis
Formalization of finite state machines with data path for the verification of high-level synthesis
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Formalization of finite state machines with data path for the verification of high-level synthesis

Borrione, D. ; Dushina, J. ; Pierre, L.

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216), 1998, p.99-102

IEEE

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