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Fast hardware-software co-simulation using VHDL models
Fast hardware-software co-simulation using VHDL models
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Fast hardware-software co-simulation using VHDL models

Tabbara, B. ; Sgroi, M. ; Sangiovanni-Vincentelli, A. ; Filippi, E. ; Lavagno, L.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.309-316

IEEE

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2
Formally verified redundancy removal
Formally verified redundancy removal
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Formally verified redundancy removal

Hendricx, S. ; Claesen, L.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078), 1999, p.150-155

IEEE

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3
On-line assertion-based verification with proven correct monitors
On-line assertion-based verification with proven correct monitors
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On-line assertion-based verification with proven correct monitors

Borrione, D. ; Miao Liu ; Morin-Allory, K. ; Ostier, P. ; Fesquet, L.

2005 International Conference on Information and Communication Technology, 2005, p.125-143

IEEE

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4
Asynchronous Assertion Monitors for multi-Clock Domain System Verification
Asynchronous Assertion Monitors for multi-Clock Domain System Verification
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Asynchronous Assertion Monitors for multi-Clock Domain System Verification

Morin-Allory, K. ; Fesquet, L. ; Borrione, D.

Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), 2006, p.98-102

IEEE

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5
Formal verification of VHDL descriptions in the Prevail environment
Formal verification of VHDL descriptions in the Prevail environment
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Formal verification of VHDL descriptions in the Prevail environment

Borrione, D.D. ; Pierre, L.V. ; Salem, A.M.

IEEE design & test of computers, 1992-06, Vol.9 (2), p.42-56

LOS ALAMITOS: IEEE Computer Society

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6
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis
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Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis

Borrione, D. ; Dushina, J. ; Pierre, L.

Proceedings of the 11th Brazilian Symposium on Integrated circuit design, 1998, p.99-99

Washington, DC, USA: IEEE Computer Society

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7
A functional approach to formal hardware verification: the MTI experience
A functional approach to formal hardware verification: the MTI experience
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A functional approach to formal hardware verification: the MTI experience

Borritone, D. ; Camurati, P. ; Paillet, J.L. ; Prinetto, P.

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 1988, p.592-595

IEEE Comput. Soc. Press

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