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1
Electronic photonic integrated circuits for high speed, high resolution, analog to digital conversion
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Electronic photonic integrated circuits for high speed, high resolution, analog to digital conversion

Kärtner, F. X ; Akiyama, S ; Barbastathis, G ; Barwicz, T ; Byun, H ; Danielson, D. T ; Gan, F ; Grawert, F ; Holzwarth, C. W ; Hoyt, J. L ; Ippen, E. P ; Kim, M ; Kimerling, L. C ; Liu, J ; Michel, J ; Olubuyide, O. O ; Orcutt, J. S ; Park, M ; Perrott, M ; Popovic, M. A ; Rackich, P. T ; Ram, R. J ; Smith, H. I ; Watts, M. R

Proceedings of SPIE, the International Society for Optical Engineering, 2006, Vol.6125, p.612503-612503-14

Bellingham (Wash.): SPIE

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2
Simulation and signal analysis of Akiyama probe applied to atomic force microscope
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Simulation and signal analysis of Akiyama probe applied to atomic force microscope

Wang, Longlong ; Lu, Mingzhen ; Guo, Tong ; Gao, Sitian ; Zhang, Huakun Ye, Shenghua ; Fei, Yetai

Proceedings of SPIE, the international society for optical engineering, 2013, Vol.8916, p.89160W-89160W-10

SPIE

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3
Characterization of Akiyama probe applied to dual-probes atomic force microscope
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Characterization of Akiyama probe applied to dual-probes atomic force microscope

Wang, Hequn ; Gao, Sitian ; Li, Wei ; Shi, Yushu ; Li, Qi ; Li, Shi ; Zhu, Zhendong Han, Sen ; Tan, JiuBin

SPIE 2016

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4
Aluminum Foam, “Alporas”: The Production Process, Properties and Applications
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Aluminum Foam, “Alporas”: The Production Process, Properties and Applications

Miyoshi, T. ; Itoh, M. ; Akiyama, S. ; Kitahara, A.

MRS proceedings, 1998, Vol.521, p.133-137, Article 133

New York, USA: Cambridge University Press

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5
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays
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Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays

Akiyama, S. ; Sekiguchi, T. ; Takemura, R. ; Kotabe, A. ; Itoh, K.

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.142-143,143a

IEEE

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6
A memory controller that reduces latency of cached SDRAM
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A memory controller that reduces latency of cached SDRAM

Miura, S. ; Akiyama, S.

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5250-5253 Vol. 5

IEEE

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7
Concordant memory design using statistical integration for the billions-transistor era
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Concordant memory design using statistical integration for the billions-transistor era

Akiyama, S. ; Sekiguchi, T. ; Kajigaya, K. ; Hanzawa, S. ; Takemura, R. ; Kawahara, T.

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.466-610 Vol. 1

IEEE

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8
High-performance silicon modulator for integrated transceivers fabricated on 300-mm wafer
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High-performance silicon modulator for integrated transceivers fabricated on 300-mm wafer

Akiyama, S. ; Baba, T. ; Imai, M. ; Mori, M. ; Usuki, T.

2014 The European Conference on Optical Communication (ECOC), 2014, p.1-3

Systematic Paris Region Systems and ICT Cluster

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9
Concordant memory-array design: an integrated statistical approach for high quality gigabit-DRAM design
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Concordant memory-array design: an integrated statistical approach for high quality gigabit-DRAM design

Akiyama, S. ; Sekiguchi, T. ; Kajigaya, K. ; Hanzawa, S. ; Takemura, R. ; Kawahara, T.

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005, 2005, p.163-166

IEEE

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10
A Hierarchical Relationship Between the Fluence Spectra and CME Kinematics in Large Solar Energetic Particle Events: A Radio Perspective
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A Hierarchical Relationship Between the Fluence Spectra and CME Kinematics in Large Solar Energetic Particle Events: A Radio Perspective

Gopalswamy, N. ; Makela, P. ; Yashiro, S. ; Thakur, N. ; Akiyama, S. ; Xie, H.

Goddard Space Flight Center 2017

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