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Refinado por: Base de dados/Biblioteca: ANTE: Abstracts in New Technology & Engineering remover assunto: Technology remover Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover
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1
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
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A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability

Rui Jia ; Hai-Gang Yang ; Lin, Colin Yu ; Rui Chen ; Xin-Gang Wang ; Zhen-Hong Guo

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-08, Vol.35 (8), p.1297-1308 [Periódico revisado por pares]

New York: IEEE

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2
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Cong, Jason ; Li, Peng ; Xiao, Bingjun ; Zhang, Peng

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-03, Vol.35 (3), p.407-418 [Periódico revisado por pares]

New York: IEEE

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3
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA
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USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA

Araujo T. Campos, Caio ; Marciano, Abner L. ; Vilela Neto, Omar P. ; Sill Torres, Frank

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-03, Vol.35 (3), p.513-517 [Periódico revisado por pares]

New York: IEEE

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4
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
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An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Wu, Chen ; Deng, Chenchen ; Liu, Leibo ; Han, Jie ; Chen, Jiqiang ; Yin, Shouyi ; Wei, Shaojun

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-08, Vol.34 (8), p.1264-1277 [Periódico revisado por pares]

New York: IEEE

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5
Field Programmable Stateful Logic Array
Field Programmable Stateful Logic Array
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Field Programmable Stateful Logic Array

Kim, Kyosun ; Shin, Sangho ; Kang, Sung-Mo

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-12, Vol.30 (12), p.1800-1813 [Periódico revisado por pares]

New York: IEEE

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6
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems
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Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems

Yanzhi Wang ; Xue Lin ; Younghyun Kim ; Naehyuck Chang ; Pedram, Massoud

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-06, Vol.33 (6), p.917-930 [Periódico revisado por pares]

New York: IEEE

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7
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy
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Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Oboril, Fabian ; Bishnoi, Rajendra ; Ebrahimi, Mojtaba ; Tahoori, Mehdi B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-03, Vol.34 (3), p.367-380 [Periódico revisado por pares]

New York: IEEE

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8
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures
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Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures

Alistar, Mirela ; Pop, Paul ; Madsen, Jan

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-05, Vol.35 (5), p.764-777 [Periódico revisado por pares]

New York: IEEE

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9
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing
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Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing

Wettin, Paul ; Kim, Ryan ; Murray, Jacob ; Xinmin Yu ; Pande, Partha P. ; Ganguly, Amlan ; Heoamlan, Deukhyoun

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-11, Vol.33 (11), p.1732-1745 [Periódico revisado por pares]

New York: IEEE

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10
Nearly-2-SAT Solutions for Segmented-Channel Routing
Nearly-2-SAT Solutions for Segmented-Channel Routing
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Nearly-2-SAT Solutions for Segmented-Channel Routing

Mukherjee, Shyamapada ; Roy, Suchismita

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-01, Vol.35 (1), p.128-140 [Periódico revisado por pares]

New York: IEEE

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