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Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer
Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer
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Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer

Xiao, Hao ; Zheng, Busheng ; Isshiki, Tsuyoshi ; Kunieda, Hiroaki

IET computers & digital techniques, 2017-01, Vol.11 (1), p.8-15 [Periódico revisado por pares]

The Institution of Engineering and Technology

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2
Exploiting memory allocations in clusterised many-core architectures
Exploiting memory allocations in clusterised many-core architectures
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Exploiting memory allocations in clusterised many-core architectures

Garibotti, Rafael ; Ost, Luciano ; Butko, Anastasiia ; Reis, Ricardo ; Gamatié, Abdoulaye ; Sassatelli, Gilles

IET computers & digital techniques, 2019-07, Vol.13 (4), p.302-311 [Periódico revisado por pares]

The Institution of Engineering and Technology

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3
Multiple sampling PSC-PWM with hierarchical control architecture for MMC-DSTATCOM
Multiple sampling PSC-PWM with hierarchical control architecture for MMC-DSTATCOM
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Multiple sampling PSC-PWM with hierarchical control architecture for MMC-DSTATCOM

Zhang, Yuxiao ; Dai, Ke ; Xu, Chen ; Kang, Yong ; Dai, Ziwei

IET electric power applications, 2019-10, Vol.13 (10), p.1431-1440 [Periódico revisado por pares]

The Institution of Engineering and Technology

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4
Decentralised resilient autonomous control architecture for dynamic microgrids
Decentralised resilient autonomous control architecture for dynamic microgrids
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Decentralised resilient autonomous control architecture for dynamic microgrids

Bani-Ahmed, Abedalsalam ; Rashidi, Mohammed ; Nasiri, Adel

IET generation, transmission & distribution, 2019-06, Vol.13 (11), p.2182-2189 [Periódico revisado por pares]

The Institution of Engineering and Technology

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5
Implementation of a low-power LVQ architecture on FPGA
Implementation of a low-power LVQ architecture on FPGA
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Implementation of a low-power LVQ architecture on FPGA

Chalbi, Najoua ; Boubaker, Mohamed ; Hedi Bedoui, Mohamed

IET circuits, devices & systems, 2017-11, Vol.11 (6), p.597-604 [Periódico revisado por pares]

The Institution of Engineering and Technology

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6
CUDA memory optimisation strategies for motion estimation
CUDA memory optimisation strategies for motion estimation
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CUDA memory optimisation strategies for motion estimation

Sayadi, Fatma Elzahra ; Chouchene, Marwa ; Bahri, Haithem ; Khemiri, Randa ; Atri, Mohamed

IET computers & digital techniques, 2019-01, Vol.13 (1), p.20-27 [Periódico revisado por pares]

The Institution of Engineering and Technology

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7
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
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Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

Trefzer, Martin A ; Walker, James A ; Bale, Simon J ; Tyrrell, Andy M

IET computers & digital techniques, 2015-07, Vol.9 (4), p.190-196 [Periódico revisado por pares]

The Institution of Engineering and Technology

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8
Compact and high-throughput parameterisable architectures for memory-based FFT algorithms
Compact and high-throughput parameterisable architectures for memory-based FFT algorithms
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Compact and high-throughput parameterisable architectures for memory-based FFT algorithms

Valencia, Daniel ; Alimohammad, Amirhossein

IET circuits, devices & systems, 2019-08, Vol.13 (5), p.696-703 [Periódico revisado por pares]

The Institution of Engineering and Technology

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9
Digital predistortion architecture with reduced ADC dynamic range
Digital predistortion architecture with reduced ADC dynamic range
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Digital predistortion architecture with reduced ADC dynamic range

Liu, Ying ; Quan, Xin ; Shao, Shihai ; Tang, Youxi

Electronics letters, 2016-03, Vol.52 (6), p.435-437 [Periódico revisado por pares]

The Institution of Engineering and Technology

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10
High-throughput and compact reconfigurable architectures for recursive filters
High-throughput and compact reconfigurable architectures for recursive filters
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High-throughput and compact reconfigurable architectures for recursive filters

Shinde, Vaishali ; Jai Kumar, Ganesh ; Valencia, Daniel ; Alimohammad, Amirhossein

IET communications, 2018-08, Vol.12 (13), p.1616-1623 [Periódico revisado por pares]

The Institution of Engineering and Technology

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