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1
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
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Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Manohararajah, V. ; Brown, S.D. ; Vranesic, Z.G.

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-11, Vol.25 (11), p.2331-2340 [Periódico revisado por pares]

New York: IEEE

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2
Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design
Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design
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Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

Shi, C.-J.R. ; Xiang-Dong Tan

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-07, Vol.20 (7), p.813-827 [Periódico revisado por pares]

New York: IEEE

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3
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC
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Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC

Tianhao Zhang ; Chakrabarty, K. ; Fair, R.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.843-858 [Periódico revisado por pares]

New York: IEEE

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4
Error bound for reduced system model by Pade approximation via the Lanczos process
Error bound for reduced system model by Pade approximation via the Lanczos process
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Error bound for reduced system model by Pade approximation via the Lanczos process

Zhaojun Bai ; Slone, R.D. ; Smith, W.T. ; Qiang Ye

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-02, Vol.18 (2), p.133-141 [Periódico revisado por pares]

New York, NY: IEEE

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5
Minimizing production test time to detect faults in analog circuits
Minimizing production test time to detect faults in analog circuits
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Minimizing production test time to detect faults in analog circuits

Milor, L. ; Sangiovanni-Vincentelli, A.L.

IEEE transactions on computer-aided design of integrated circuits and systems, 1994, Vol.13 (6), p.796-813 [Periódico revisado por pares]

New York, NY: IEEE

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6
On Delay Fault Testing in Logic Circuits
On Delay Fault Testing in Logic Circuits
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On Delay Fault Testing in Logic Circuits

Chin Jen Lin ; Reddy, S.M.

IEEE transactions on computer-aided design of integrated circuits and systems, 1987-09, Vol.6 (5), p.694-703 [Periódico revisado por pares]

New York, NY: IEEE

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7
Electrical analysis and modeling of floating-gate fault
Electrical analysis and modeling of floating-gate fault
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Electrical analysis and modeling of floating-gate fault

Renovell, M. ; Cambon, G.N.

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-11, Vol.11 (11), p.1450-1458 [Periódico revisado por pares]

NEW YORK: IEEE

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8
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices
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Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

Diaz, C.H. ; Sung-Mo Kang ; Duvvury, C.

IEEE transactions on computer-aided design of integrated circuits and systems, 1994, Vol.13 (4), p.482-493 [Periódico revisado por pares]

New York, NY: IEEE

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9
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults
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A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults

Gharaybeh, M.A. ; Bushnell, M.L. ; Agrawal, V.D.

IEEE transactions on computer-aided design of integrated circuits and systems, 1998-09, Vol.17 (9), p.873-876 [Periódico revisado por pares]

New York, NY: IEEE

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10
Test embedding with discrete logarithms
Test embedding with discrete logarithms
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Test embedding with discrete logarithms

Lempel, M. ; Gupta, S.K. ; Breuer, M.A.

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-05, Vol.14 (5), p.554-566 [Periódico revisado por pares]

New York, NY: IEEE

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