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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Sun, Hanbo ; Zhu, Zhenhua ; Wang, Chenyu ; Ning, Xuefei ; Dai, Guohao ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search
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CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search

Hassantabar, Shayan ; Dai, Xiaoliang ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4975-4990 [Periódico revisado por pares]

New York: IEEE

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3
M²NAS: Joint Neural Architecture Optimization System With Network Transmission
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M²NAS: Joint Neural Architecture Optimization System With Network Transmission

Wang, Lanfei ; Xie, Lingxi ; Bi, Kaifeng ; Zhao, Kaili ; Guo, Jun ; Tian, Qi

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-08, Vol.42 (8), p.2631-2642 [Periódico revisado por pares]

New York: IEEE

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4
TUTOR: Training Neural Networks Using Decision Rules as Model Priors
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TUTOR: Training Neural Networks Using Decision Rules as Model Priors

Hassantabar, Shayan ; Terway, Prerit ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-02, Vol.42 (2), p.483-496 [Periódico revisado por pares]

New York: IEEE

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5
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures
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MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures

Zhu, Zhenhua ; Sun, Hanbo ; Xie, Tongxin ; Zhu, Yu ; Dai, Guohao ; Xia, Lixue ; Niu, Dimin ; Chen, Xiaoming ; Hu, X. Sharon ; Cao, Yu ; Xie, Yuan ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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6
Nearly-2-SAT Solutions for Segmented-Channel Routing
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Nearly-2-SAT Solutions for Segmented-Channel Routing

Mukherjee, Shyamapada ; Roy, Suchismita

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-01, Vol.35 (1), p.128-140 [Periódico revisado por pares]

New York: IEEE

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7
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture
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A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

Hassan, Sahil ; Dattilo, Parker ; Akoglu, Ali

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

IEEE

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8
Realization and Hardware Implementation of Gating Units for Long Short Term Memory Network using Hyperbolic Sine Functions
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Realization and Hardware Implementation of Gating Units for Long Short Term Memory Network using Hyperbolic Sine Functions

Joseph, Tresa ; S., Bindiya T.

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

New York: IEEE

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9
Distributed Deep Learning Optimization of Heat Equation Inverse Problem Solvers
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Distributed Deep Learning Optimization of Heat Equation Inverse Problem Solvers

Wang, Zhuowei ; Yang, Le ; Lin, Haoran ; Zhao, Genping ; Liu, Zixuan ; Song, Xiaoyu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

New York: IEEE

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10
Synthesis of Active Cell Balancing Architectures for Battery Packs
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Synthesis of Active Cell Balancing Architectures for Battery Packs

Lukasiewycz, Martin ; Kauer, Matthias ; Steinhorst, Sebastian

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-11, Vol.35 (11), p.1876-1889 [Periódico revisado por pares]

New York: IEEE

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