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Refinado por: Base de dados/Biblioteca: IEEE Electronic Library (IEL) Journals remover Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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11
Computing in Memory With Spin-Transfer Torque Magnetic RAM
Computing in Memory With Spin-Transfer Torque Magnetic RAM
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Computing in Memory With Spin-Transfer Torque Magnetic RAM

Jain, Shubham ; Ranjan, Ashish ; Roy, Kaushik ; Raghunathan, Anand

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483 [Periódico revisado por pares]

IEEE

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12
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
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Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Eshraghian, Kamran ; Kyoung-Rok Cho ; Kavehei, Omid ; Soon-Ku Kang ; Abbott, Derek ; Sung-Mo Steve Kang

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1407-1417 [Periódico revisado por pares]

New York, NY: IEEE

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13
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads
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Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

Ali, Mustafa ; Roy, Sourjya ; Saxena, Utkarsh ; Sharma, Tanvi ; Raghunathan, Anand ; Roy, Kaushik

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1-16 [Periódico revisado por pares]

New York: IEEE

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14
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates
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DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

Ullah, Inayat ; Ullah, Zahid ; Afzaal, Umar ; Lee, Jeong-A

IEEE transactions on very large scale integration (VLSI) systems, 2019-06, Vol.27 (6), p.1298-1307 [Periódico revisado por pares]

New York: IEEE

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15
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications
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High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

Lin, Zhiting ; Chen, Min ; Sun, Peng ; Wu, Xiulong ; Zhao, Qiang ; Lu, Wenjuan ; Peng, Chunyu

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.522-531 [Periódico revisado por pares]

New York: IEEE

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16
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks
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PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

Chang, Liang ; Ma, Xin ; Wang, Zhaohao ; Zhang, Youguang ; Xie, Yuan ; Zhao, Weisheng

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2668-2679 [Periódico revisado por pares]

New York: IEEE

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17
A 2-D Calibration Scheme for Resistive Nonvolatile Memories
A 2-D Calibration Scheme for Resistive Nonvolatile Memories
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A 2-D Calibration Scheme for Resistive Nonvolatile Memories

Lee, Albert ; Jagannathan, Raahul ; Wu, Di ; Wang, Kang L.

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1371-1377 [Periódico revisado por pares]

New York: IEEE

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18
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches
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Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

Agarwal, Sukarn ; Kapoor, Hemangee K.

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.1881-1894 [Periódico revisado por pares]

New York: IEEE

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19
PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems
PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems
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PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

Niu, Na ; Fu, Fangfa ; Yang, Bing ; Wang, Qiang ; Li, Xinpeng ; Lai, Fengchang ; Wang, Jinxiang

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1685-1692 [Periódico revisado por pares]

New York: IEEE

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20
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed
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Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

Xu, Wei ; Zhang, Tong ; Chen, Yiran

IEEE transactions on very large scale integration (VLSI) systems, 2010-01, Vol.18 (1), p.66-74 [Periódico revisado por pares]

New York, NY: IEEE

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