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In-Memory Computing With Double Word Lines and Three Read Ports for Four OperandsLin, Zhiting ; Zhan, Honglan ; Li, Xuan ; Peng, Chunyu ; Lu, Wenjuan ; Wu, Xiulong ; Chen, JunningIEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile MemoryJingtong Hu ; Xue, C. J. ; Qingfeng Zhuge ; Wei-Che Tseng ; Sha, E. H.IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-MemoryChen, Yuzong ; Lu, Lu ; Kim, Bongjin ; Kim, Tony Tae-HyoungIEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2636-2649 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like ArchitectureLuo, Yuan-Chun ; Lu, Anni ; Luo, Yandong ; Chang, Sou-Chi ; Avci, Uygar ; Yu, ShimengIEEE transactions on very large scale integration (VLSI) systems, 2024-09, Vol.32 (9), p.1696-1703 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Resource-Efficient SRAM-Based Ternary Content Addressable MemoryAhmed, Ali ; Kyungbae Park ; Sanghyeon BaegIEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1583-1587 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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Boosting NVDIMM Performance With a Lightweight Caching AlgorithmTsao, Che-Wei ; Chang, Yuan-Hao ; Kuo, Tei-WeiIEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority GatesReuben, John ; Pechmann, StefanIEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1108-1121 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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DART: A Framework for Determining Approximation Levels in an Approximable Memory HierarchyYarmand, Roohollah ; Kamal, Mehdi ; Afzali-Kusha, Ali ; Pedram, MassoudIEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.273-286 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network AcceleratorsPutra, Rachmad Vidya Wicaksana ; Hanif, Muhammad Abdullah ; Shafique, MuhammadIEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Computing in Memory With Spin-Transfer Torque Magnetic RAMJain, Shubham ; Ranjan, Ashish ; Roy, Kaushik ; Raghunathan, AnandIEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483 [Periódico revisado por pares]IEEETexto completo disponível |