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1
Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs
Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs
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Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

Chang, Wen-Teng ; Shih, Cheng-Ting ; Wu, Jhao-Lin ; Lin, Shih-Wei ; Cin, Li-Gong ; Yeh, Wen-Kuan

IEEE transactions on nanotechnology, 2018-01, Vol.17 (1), p.36-40 [Periódico revisado por pares]

New York: IEEE

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2
Improved Contact Resistivity and Transconductance for Sub-10 nm FinFET Technology by Laser-Induced Contact Silicide
Improved Contact Resistivity and Transconductance for Sub-10 nm FinFET Technology by Laser-Induced Contact Silicide
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Improved Contact Resistivity and Transconductance for Sub-10 nm FinFET Technology by Laser-Induced Contact Silicide

Lai, Guan-Ting ; Peng, Hao-Kai ; Chen, Yi-Fan ; Teng, Shih-Chieh ; Chou, Chuan-Pu ; Kao, Yu-Cheng ; Wu, Pin-Jiun ; Wu, Yung-Hsien

IEEE transactions on nanotechnology, 2021, Vol.20, p.761-764 [Periódico revisado por pares]

New York: IEEE

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3
Simulation Investigation of the Diffusion Enhancement Effects in FinFET With Graded Fin Width
Simulation Investigation of the Diffusion Enhancement Effects in FinFET With Graded Fin Width
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Simulation Investigation of the Diffusion Enhancement Effects in FinFET With Graded Fin Width

Zhang, Maolin ; Guo, Yufeng ; Chen, Jing ; Zhang, Jun ; Tong, Yi

IEEE transactions on nanotechnology, 2019, Vol.18, p.700-703 [Periódico revisado por pares]

IEEE

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4
A New Short-Channel-Effect-Degraded Subthreshold Behavior Model for Double-Fin Multichannel FETs (DFMcFETs)
A New Short-Channel-Effect-Degraded Subthreshold Behavior Model for Double-Fin Multichannel FETs (DFMcFETs)
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A New Short-Channel-Effect-Degraded Subthreshold Behavior Model for Double-Fin Multichannel FETs (DFMcFETs)

Te-Kuang Chiang

IEEE transactions on nanotechnology, 2017-01, Vol.16 (1), p.16-22 [Periódico revisado por pares]

New York: IEEE

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5
The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs
The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs
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The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs

Liao, M.-H ; Chen, P.-G

IEEE transactions on nanotechnology, 2015-07, Vol.14 (4), p.657-659 [Periódico revisado por pares]

New York: IEEE

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6
Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory
Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory
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Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory

Yeh, Mu-Shih ; Wu, Yung-Chun ; Liu, Kuan-Cheng ; Hung, Min-Feng ; Jhan ; Lu, Nan-Heng ; Chung, Ming-Hsien ; Wu, Min-Hsin

IEEE transactions on nanotechnology, 2014-07, Vol.13 (4), p.814-819 [Periódico revisado por pares]

New York: IEEE

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7
Channel Stress and Ballistic Performance Advantages of Gate-All-Around FETs and Inserted-Oxide FinFETs
Channel Stress and Ballistic Performance Advantages of Gate-All-Around FETs and Inserted-Oxide FinFETs
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Channel Stress and Ballistic Performance Advantages of Gate-All-Around FETs and Inserted-Oxide FinFETs

Connelly, Daniel ; Peng Zheng ; Liu, Tsu-Jae King

IEEE transactions on nanotechnology, 2017-03, Vol.16 (2), p.209-216 [Periódico revisado por pares]

IEEE

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8
HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET
HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET
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HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

Majumdar, Kausik ; Majhi, Prashant ; Bhat, Navakanta ; Jammy, Raj

IEEE transactions on nanotechnology, 2010-05, Vol.9 (3), p.342-344 [Periódico revisado por pares]

New York, NY: IEEE

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9
A New Threshold Voltage Model for Short-Channel Junctionless Inverted T-Shaped Gate FETs (JLITFET)
A New Threshold Voltage Model for Short-Channel Junctionless Inverted T-Shaped Gate FETs (JLITFET)
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A New Threshold Voltage Model for Short-Channel Junctionless Inverted T-Shaped Gate FETs (JLITFET)

Chiang, Te-Kuang

IEEE transactions on nanotechnology, 2016-05, Vol.15 (3), p.442-447 [Periódico revisado por pares]

New York: IEEE

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10
Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET
Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET
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Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET

Trivedi, Amit Ranjan ; Mukhopadhyay, Saibal

IEEE transactions on nanotechnology, 2014-07, Vol.13 (4), p.627-629 [Periódico revisado por pares]

New York: IEEE

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