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Refinado por: Base de dados/Biblioteca: IEEE Electronic Library (IEL) Journals remover Nome da Publicação: Ieee Transactions On Circuits And Systems. I, Regular Papers remover
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1
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
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X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Agrawal, Amogh ; Jaiswal, Akhilesh ; Lee, Chankyu ; Roy, Kaushik

IEEE transactions on circuits and systems. I, Regular papers, 2018-12, Vol.65 (12), p.4219-4232 [Periódico revisado por pares]

New York: IEEE

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2
IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array
IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array
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IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Ali, Mustafa ; Jaiswal, Akhilesh ; Kodge, Sangamesh ; Agrawal, Amogh ; Chakraborty, Indranil ; Roy, Kaushik

IEEE transactions on circuits and systems. I, Regular papers, 2020-08, Vol.67 (8), p.2521-2531 [Periódico revisado por pares]

New York: IEEE

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3
Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices
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Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

Jhang, Chuan-Jia ; Xue, Cheng-Xin ; Hung, Je-Min ; Chang, Fu-Chun ; Chang, Meng-Fan

IEEE transactions on circuits and systems. I, Regular papers, 2021-05, Vol.68 (5), p.1773-1786 [Periódico revisado por pares]

New York: IEEE

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4
RRAM for Compute-in-Memory: From Inference to Training
RRAM for Compute-in-Memory: From Inference to Training
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RRAM for Compute-in-Memory: From Inference to Training

Yu, Shimeng ; Shim, Wonbo ; Peng, Xiaochen ; Luo, Yandong

IEEE transactions on circuits and systems. I, Regular papers, 2021-07, Vol.68 (7), p.2753-2765 [Periódico revisado por pares]

New York: IEEE

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5
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors
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A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

Si, Xin ; Chang, Meng-Fan ; Khwa, Win-San ; Chen, Jia-Jing ; Li, Jia-Fang ; Sun, Xiaoyu ; Liu, Rui ; Yu, Shimeng ; Yamauchi, Hiroyuki ; Li, Qiang

IEEE transactions on circuits and systems. I, Regular papers, 2019-11, Vol.66 (11), p.4172-4185 [Periódico revisado por pares]

New York: IEEE

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6
A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
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A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things

Du, Li ; Du, Yuan ; Li, Yilei ; Su, Junjie ; Kuan, Yen-Cheng ; Liu, Chun-Chen ; Chang, Mau-Chung Frank

IEEE transactions on circuits and systems. I, Regular papers, 2018-01, Vol.65 (1), p.198-208 [Periódico revisado por pares]

New York: IEEE

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7
Research Progress on Memristor: From Synapses to Computing Systems
Research Progress on Memristor: From Synapses to Computing Systems
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Research Progress on Memristor: From Synapses to Computing Systems

Yang, Xiaoxuan ; Taylor, Brady ; Wu, Ailong ; Chen, Yiran ; Chua, Leon O.

IEEE transactions on circuits and systems. I, Regular papers, 2022-05, Vol.69 (5), p.1845-1857 [Periódico revisado por pares]

New York: IEEE

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8
Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits
Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits
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Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Krestinskaya, Olga ; Salama, Khaled Nabil ; James, Alex Pappachen

IEEE transactions on circuits and systems. I, Regular papers, 2019-02, Vol.66 (2), p.719-732 [Periódico revisado por pares]

New York: IEEE

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9
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks
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A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks

Zhuang, Haoyu ; Xi, Xiaodan ; Sun, Nan ; Orshansky, Michael

IEEE transactions on circuits and systems. I, Regular papers, 2020-01, Vol.67 (1), p.135-144 [Periódico revisado por pares]

New York: IEEE

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10
Efficient Hardware Architectures for Deep Convolutional Neural Network
Efficient Hardware Architectures for Deep Convolutional Neural Network
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Efficient Hardware Architectures for Deep Convolutional Neural Network

Wang, Jichen ; Lin, Jun ; Wang, Zhongfeng

IEEE transactions on circuits and systems. I, Regular papers, 2018-06, Vol.65 (6), p.1941-1953 [Periódico revisado por pares]

New York: IEEE

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