skip to main content
Idioma:
Resultados 1 2 3 4 next page
Mostrar Somente
Refinado por: Base de dados/Biblioteca: ACM Digital Library remover Base de dados/Biblioteca: Recercat remover
Result Number Material Type Add to My Shelf Action Record Details and Options
1
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Cook, Henry ; Moreto, Miquel ; Bird, Sarah ; Dao, Khanh ; Patterson, David A. ; Asanovic, Krste

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.308-319

New York, NY, USA: ACM

Texto completo disponível

Citações Citado por
2
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

Alvarez, Lluc ; Vilanova, Lluís ; Moreto, Miquel ; Casas, Marc ; Gonzàlez, Marc ; Martorell, Xavier ; Navarro, Nacho ; Ayguadé, Eduard ; Valero, Mateo

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015, p.720-732

New York, NY, USA: ACM

Texto completo disponível

Citações Citado por
3
An Analytical Model for Loc/ID Mappings Caches
An Analytical Model for Loc/ID Mappings Caches
Material Type:
Artigo 		Adicionar ao Meu Espaço

An Analytical Model for Loc/ID Mappings Caches

Coras, Florin ; Domingo-Pascual, Jordi ; Lewis, Darrel ; Cabellos-Aparicio, Albert

IEEE/ACM transactions on networking, 2016-02, Vol.24 (1), p.506-516 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
4
Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling
Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime scheduling

Caheny, Paul ; Casas, Marc ; Moreto Planas, Miquel ; Gloaguen, Hervé ; Saintes, Maxime ; Ayguadé Parra, Eduard ; Labarta Mancho, Jesús José ; Valero Cortés, Mateo

Institute of Electrical and Electronics Engineers (IEEE) 2016

Texto completo disponível

Citações Citado por
5
Runtime-guided management of scratchpad memories in multicore architectures
Runtime-guided management of scratchpad memories in multicore architectures
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Runtime-guided management of scratchpad memories in multicore architectures

Álvarez Martí, Lluc ; Moreto Planas, Miquel ; Casas Guix, Marc ; Castillo Villar, Emilio ; Martorell Bofill, Xavier ; Labarta Mancho, Jesús José ; Ayguadé Parra, Eduard ; Valero Cortés, Mateo

Institute of Electrical and Electronics Engineers (IEEE) 2015

Texto completo disponível

Citações Citado por
6
Random Modulo: A new processor cache design for real-time critical systems
Random Modulo: A new processor cache design for real-time critical systems
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Random Modulo: A new processor cache design for real-time critical systems

Hernández, Carles ; Abella Ferrer, Jaume ; Gianarro, Andrea ; Andersson, Jan ; Cazorla Almeida, Francisco Javier

Institute of Electrical and Electronics Engineers (IEEE) 2016

Texto completo disponível

Citações Citado por
7
A Dynamically Adaptable Hardware Transactional Memory
A Dynamically Adaptable Hardware Transactional Memory
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

A Dynamically Adaptable Hardware Transactional Memory

Lupon, Marc ; Magklis, Grigorios ; Gonzalez, Antonio

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.27-38

Washington, DC, USA: IEEE Computer Society

Texto completo disponível

Citações Citado por
8
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems

Slijepcevic, Mladen ; Kosmidis, Leonidas ; Abella, Jaume ; Quiñones, Eduardo ; Cazorla, Francisco J.

Proceedings of the 51st Annual Design Automation Conference, 2014, p.1-6

New York, NY, USA: ACM

Texto completo disponível

Citações Citado por
9
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy

Jaksic, Zoran ; Canal Corretger, Ramon

European Interactive Digital Advertising Alliance (EDAA) 2014

Texto completo disponível

Citações Citado por
10
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery

Lupon, M. ; Magklis, G. ; Gonzalez, A.

2009 18th International Conference on Parallel Architectures and Compilation Techniques, 2009, p.293-302

IEEE

Texto completo disponível

Citações Citado por
Resultados 1 2 3 4 next page

  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

Buscando em bases de dados remotas. Favor aguardar.