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1 |
Material Type: Ata de Congresso
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A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsivenessCook, Henry ; Moreto, Miquel ; Bird, Sarah ; Dao, Khanh ; Patterson, David A. ; Asanovic, KrsteProceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.308-319New York, NY, USA: ACMTexto completo disponível |
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Material Type: Ata de Congresso
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Coherence protocol for transparent management of scratchpad memories in shared memory manycore architecturesAlvarez, Lluc ; Vilanova, Lluís ; Moreto, Miquel ; Casas, Marc ; Gonzàlez, Marc ; Martorell, Xavier ; Navarro, Nacho ; Ayguadé, Eduard ; Valero, MateoProceedings of the 42nd Annual International Symposium on Computer Architecture, 2015, p.720-732New York, NY, USA: ACMTexto completo disponível |
3 |
Material Type: Artigo
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An Analytical Model for Loc/ID Mappings CachesCoras, Florin ; Domingo-Pascual, Jordi ; Lewis, Darrel ; Cabellos-Aparicio, AlbertIEEE/ACM transactions on networking, 2016-02, Vol.24 (1), p.506-516 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Reducing cache coherence traffic with hierarchical directory cache and NUMA-aware runtime schedulingCaheny, Paul ; Casas, Marc ; Moreto Planas, Miquel ; Gloaguen, Hervé ; Saintes, Maxime ; Ayguadé Parra, Eduard ; Labarta Mancho, Jesús José ; Valero Cortés, MateoInstitute of Electrical and Electronics Engineers (IEEE) 2016Texto completo disponível |
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Material Type: Ata de Congresso
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Runtime-guided management of scratchpad memories in multicore architecturesÁlvarez Martí, Lluc ; Moreto Planas, Miquel ; Casas Guix, Marc ; Castillo Villar, Emilio ; Martorell Bofill, Xavier ; Labarta Mancho, Jesús José ; Ayguadé Parra, Eduard ; Valero Cortés, MateoInstitute of Electrical and Electronics Engineers (IEEE) 2015Texto completo disponível |
6 |
Material Type: Ata de Congresso
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Random Modulo: A new processor cache design for real-time critical systemsHernández, Carles ; Abella Ferrer, Jaume ; Gianarro, Andrea ; Andersson, Jan ; Cazorla Almeida, Francisco JavierInstitute of Electrical and Electronics Engineers (IEEE) 2016Texto completo disponível |
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Material Type: Ata de Congresso
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A Dynamically Adaptable Hardware Transactional MemoryLupon, Marc ; Magklis, Grigorios ; Gonzalez, Antonio2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.27-38Washington, DC, USA: IEEE Computer SocietyTexto completo disponível |
8 |
Material Type: Ata de Congresso
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Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore SystemsSlijepcevic, Mladen ; Kosmidis, Leonidas ; Abella, Jaume ; Quiñones, Eduardo ; Cazorla, Francisco J.Proceedings of the 51st Annual Design Automation Conference, 2014, p.1-6New York, NY, USA: ACMTexto completo disponível |
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Material Type: Ata de Congresso
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DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energyJaksic, Zoran ; Canal Corretger, RamonEuropean Interactive Digital Advertising Alliance (EDAA) 2014Texto completo disponível |
10 |
Material Type: Ata de Congresso
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FASTM: A Log-based Hardware Transactional Memory with Fast Abort RecoveryLupon, M. ; Magklis, G. ; Gonzalez, A.2009 18th International Conference on Parallel Architectures and Compilation Techniques, 2009, p.293-302IEEETexto completo disponível |