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Refinado por: Nome da Publicação: Ieice Transactions On Fundamentals Of Electronics, Communications And Computer Sciences remover idioma: Japonês remover
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Sorting Matrix Architecture for Continuous Data Sequences
Sorting Matrix Architecture for Continuous Data Sequences
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Sorting Matrix Architecture for Continuous Data Sequences

XUE, Meiting ; ZHANG, Huan ; LI, Weijun ; YU, Feng

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2020/02/01, Vol.E103.A(2), pp.542-546 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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2
Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
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Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes

CHANG, Yanyan ; ZHANG, Wei ; WANG, Hao ; SHI, Lina ; LIU, Yanyan

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2024/01/01, Vol.E107.A(1), pp.174-177 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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3
U-Net Architecture for Ancient Handwritten Chinese Character Detection in Han Dynasty Wooden Slips
U-Net Architecture for Ancient Handwritten Chinese Character Detection in Han Dynasty Wooden Slips
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U-Net Architecture for Ancient Handwritten Chinese Character Detection in Han Dynasty Wooden Slips

SHIMOYAMA, Hojun ; YOSHIDA, Soh ; FUJITA, Takao ; MUNEYASU, Mitsuji

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2023/11/01, Vol.E106.A(11), pp.1406-1415 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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4
Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding
Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding
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Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding

LU, Tongwei ; ZHANG, Hao ; MIN, Feng ; JIA, Shihai

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/12/01, Vol.E105.A(12), pp.1621-1625 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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5
An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation
An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation
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An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation

KASAUKA, Dabwitso ; SUGIYAMA, Kenta ; TSUTSUI, Hiroshi ; OKUHATA, Hiroyuki ; MIYANAGA, Yoshikazu

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/06/01, Vol.E102.A(6), pp.775-782 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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6
Scalable and Parameterized Architecture for Efficient Stream Mining
Scalable and Parameterized Architecture for Efficient Stream Mining
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Scalable and Parameterized Architecture for Efficient Stream Mining

ZHANG, Li ; LI, Dawei ; ZOU, Xuecheng ; HU, Yu ; XU, Xiaowei

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/01/01, Vol.E101.A(1), pp.219-231 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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7
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
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High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA

RANAWAKA, Piyumal ; EKPANYAPONG, Mongkol ; TAVARES, Adriano ; DAILEY, Mathew ; ATHIKULWONGSE, Krit ; SILVA, Vitor

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1792-1803 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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8
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing

XU, Hongjie ; SHIOMI, Jun ; ISHIHARA, Tohru ; ONODERA, Hidetoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1741-1750 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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9
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
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Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble

MITSUNARI, Koichi ; YU, Jaehoon ; ONOYE, Takao ; HASHIMOTO, Masanori

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/09/01, Vol.E101.A(9), pp.1298-1307 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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10
Low-Latency Low-Cost Architecture for Square and Cube Roots
Low-Latency Low-Cost Architecture for Square and Cube Roots
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Low-Latency Low-Cost Architecture for Square and Cube Roots

JO, Jihyuck ; PARK, In-Cheol

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2017/09/01, Vol.E100.A(9), pp.1951-1955 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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