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Low-Power and Area-Efficient Carry Select Adder
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Low-Power and Area-Efficient Carry Select Adder

Ramkumar, B. ; Kittur, H. M.

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.371-375 [Periódico revisado por pares]

New York, NY: IEEE

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2
Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems
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Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems

Chicca, Elisabetta ; Stefanini, Fabio ; Bartolozzi, Chiara ; Indiveri, Giacomo

Proceedings of the IEEE, 2014-09, Vol.102 (9), p.1367-1388 [Periódico revisado por pares]

New York, NY: IEEE

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3
"It's a small world after all": NoC performance optimization via long-range link insertion
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"It's a small world after all": NoC performance optimization via long-range link insertion

Ogras, U.Y. ; Marculescu, R.

IEEE transactions on very large scale integration (VLSI) systems, 2006-07, Vol.14 (7), p.693-706 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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4
Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number
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Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number

CHEN, Tse-Wei ; CHIEN, Shao-Yi

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1336-1345 [Periódico revisado por pares]

New York, NY: IEEE

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5
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

Jing Li ; Ndai, Patrick ; Goel, Ashish ; Salahuddin, Sayeef ; Roy, Kaushik

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1710-1723 [Periódico revisado por pares]

New York, NY: IEEE

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6
Architectures of Flexible Symmetric Key Crypto Engines—A Survey: From Hardware Coprocessor to Multi-Crypto-Processor System on Chip
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Architectures of Flexible Symmetric Key Crypto Engines—A Survey: From Hardware Coprocessor to Multi-Crypto-Processor System on Chip

BOSSUET, Lilian ; GRAND, Michael ; GASPAR, Lubos ; FISCHER, Viktor ; GOGNIAT, Guy

ACM computing surveys, 2013-08, Vol.45 (4), p.1-32 [Periódico revisado por pares]

New York, NY: Association for Computing Machinery

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7
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
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A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

KAO, Chao-Yang ; LIN, Youn-Long

IEEE transactions on very large scale integration (VLSI) systems, 2010-06, Vol.18 (6), p.866-874 [Periódico revisado por pares]

New York, NY: IEEE

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8
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Zhu, Ning ; Goh, Wang Ling ; Zhang, Weija ; Yeo, Kiat Seng ; Kong, Zhi Hui

IEEE transactions on very large scale integration (VLSI) systems, 2010-08, Vol.18 (8), p.1225-1229 [Periódico revisado por pares]

New York, NY: IEEE

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9
Visual Pattern Extraction Using Energy-Efficient "2-PCM Synapse" Neuromorphic Architecture
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Visual Pattern Extraction Using Energy-Efficient "2-PCM Synapse" Neuromorphic Architecture

Bichler, O. ; Suri, M. ; Querlioz, D. ; Vuillaume, D. ; DeSalvo, B. ; Gamrat, C.

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2206-2214 [Periódico revisado por pares]

New York, NY: IEEE

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10
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories
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A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

Park, Ki-Tae ; Kang, Myounggon ; Kim, Doogon ; Hwang, Soon-Wook ; Choi, Byung Yong ; Lee, Yeong-Taek ; Kim, Changhyun ; Kim, Kinam

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.919-928 [Periódico revisado por pares]

New York, NY: IEEE

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