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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover assunto: Software remover
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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Ni, Tianming ; Yao, Yao ; Chang, Hao ; Lu, Lin ; Liang, Huaguo ; Yan, Aibin ; Huang, Zhengfeng ; Wen, Xiaoqing

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951 [Periódico revisado por pares]

New York: IEEE

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2
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Akopyan, Filipp ; Sawada, Jun ; Cassidy, Andrew ; Alvarez-Icaza, Rodrigo ; Arthur, John ; Merolla, Paul ; Imam, Nabil ; Nakamura, Yutaka ; Datta, Pallab ; Gi-Joon Nam ; Taba, Brian ; Beakes, Michael ; Brezzo, Bernard ; Kuang, Jente B. ; Manohar, Rajit ; Risk, William P. ; Jackson, Bryan ; Modha, Dharmendra S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-10, Vol.34 (10), p.1537-1557 [Periódico revisado por pares]

New York: IEEE

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3
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment
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Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment

Sarkar, Ardhendu ; Ghosh, Surajeet

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-02, p.1-1 [Periódico revisado por pares]

IEEE

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4
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits
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Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits

Ding, Jingwen ; Yamashita, Shigeru

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-05, Vol.39 (5), p.1045-1058 [Periódico revisado por pares]

New York: IEEE

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5
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
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Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

Zhang, Chen ; Sun, Guangyu ; Fang, Zhenman ; Zhou, Peipei ; Pan, Peichen ; Cong, Jason

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-11, Vol.38 (11), p.2072-2085 [Periódico revisado por pares]

New York: IEEE

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6
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification
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ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Grandmaison, Arnaud de ; Heydemann, Karine ; Meunier, Quentin L.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.3733-3744 [Periódico revisado por pares]

New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)

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7
From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration
From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration
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From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration

Zhuo, Cheng ; Unda, Kassan ; Shi, Yiyu ; Shih, Wei-Kai

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1291-1304 [Periódico revisado por pares]

New York: IEEE

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8
Microprocessor Optimizations for the Internet of Things: A Survey
Microprocessor Optimizations for the Internet of Things: A Survey
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Microprocessor Optimizations for the Internet of Things: A Survey

Adegbija, Tosiron ; Rogacs, Anita ; Patel, Chandrakant ; Gordon-Ross, Ann

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-01, Vol.37 (1), p.7-20 [Periódico revisado por pares]

IEEE

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9
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW
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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki, Simon ; Rohou, Erven ; Derrien, Steven

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-10, Vol.38 (10), p.1872-1885 [Periódico revisado por pares]

IEEE

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10
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture
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X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture

Akbari, Omid ; Kamal, Mehdi ; Afzali-Kusha, Ali ; Pedram, Massoud ; Shafique, Muhammad

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2558-2571 [Periódico revisado por pares]

New York: IEEE

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