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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover assunto: Software remover
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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Periódico revisado por pares]

New York: IEEE

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2
Read Performance: The Newest Barrier in Scaled STT-RAM
Read Performance: The Newest Barrier in Scaled STT-RAM
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Read Performance: The Newest Barrier in Scaled STT-RAM

Yaojun Zhang ; Yong Li ; Zhenyu Sun ; Hai Li ; Yiran Chen ; Jones, Alex K.

IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1170-1174 [Periódico revisado por pares]

IEEE

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3
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
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An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks

Wang, Yizhi ; Lin, Jun ; Wang, Zhongfeng

IEEE transactions on very large scale integration (VLSI) systems, 2018-02, Vol.26 (2), p.280-293 [Periódico revisado por pares]

IEEE

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4
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
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Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder

Dalloo, Ayad ; Najafi, Ardalan ; Garcia-Ortiz, Alberto

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1595-1599 [Periódico revisado por pares]

New York: IEEE

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5
Architecture of Cobweb-Based Redundant TSV for Clustered Faults
Architecture of Cobweb-Based Redundant TSV for Clustered Faults
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Architecture of Cobweb-Based Redundant TSV for Clustered Faults

Ni, Tianming ; Liu, Dongsheng ; Xu, Qi ; Huang, Zhengfeng ; Liang, Huaguo ; Yan, Aibin

IEEE transactions on very large scale integration (VLSI) systems, 2020-07, Vol.28 (7), p.1736-1739 [Periódico revisado por pares]

New York: IEEE

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6
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
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A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

Nguyen, Duy Thanh ; Nguyen, Tuan Nghia ; Kim, Hyun ; Lee, Hyuk-Jae

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1861-1873 [Periódico revisado por pares]

New York: IEEE

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7
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions
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PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions

Dong, Hongxi ; Wang, Manzhen ; Luo, Yuanyong ; Zheng, Muhan ; An, Mengyu ; Ha, Yajun ; Pan, Hongbing

IEEE transactions on very large scale integration (VLSI) systems, 2020-09, Vol.28 (9), p.2014-2027 [Periódico revisado por pares]

New York: IEEE

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8
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
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An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs

Zhu, Chaoyang ; Huang, Kejie ; Yang, Shuyuan ; Zhu, Ziqi ; Zhang, Hejia ; Shen, Haibin

IEEE transactions on very large scale integration (VLSI) systems, 2020-09, Vol.28 (9), p.1953-1965 [Periódico revisado por pares]

New York: IEEE

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9
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption
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Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption

Reis, Dayane ; Takeshita, Jonathan ; Jung, Taeho ; Niemier, Michael ; Hu, Xiaobo Sharon

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2300-2313 [Periódico revisado por pares]

New York: IEEE

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10
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
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RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

Zendegani, Reza ; Kamal, Mehdi ; Bahadori, Milad ; Afzali-Kusha, Ali ; Pedram, Massoud

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.393-401 [Periódico revisado por pares]

New York: IEEE

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