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1
Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor
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Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor

Bandyopadhyay, S. ; Chandrakasan, A. P.

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2199-2215 [Periódico revisado por pares]

New York, NY: IEEE

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2
Low-Power and Area-Efficient Carry Select Adder
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Low-Power and Area-Efficient Carry Select Adder

Ramkumar, B. ; Kittur, H. M.

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.371-375 [Periódico revisado por pares]

New York, NY: IEEE

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3
Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems
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Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems

KUANG, Shiann-Rong ; WANG, Jiun-Ping ; CHANG, Kai-Cheng ; HSU, Huan-Wei

IEEE transactions on very large scale integration (VLSI) systems, 2013-11, Vol.21 (11), p.1999-2009 [Periódico revisado por pares]

New York, NY: IEEE

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4
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes
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Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes

Zhang, Xinmiao ; Cai, Fang

IEEE transactions on very large scale integration (VLSI) systems, 2011-07, Vol.19 (7), p.1229-1238 [Periódico revisado por pares]

New York, NY: IEEE

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5
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy
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Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

Jongsun Park ; Jung Hwan Choi ; Roy, Kaushik

IEEE transactions on very large scale integration (VLSI) systems, 2010-05, Vol.18 (5), p.787-793 [Periódico revisado por pares]

New York, NY: IEEE

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6
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
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A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

Ishihara, S. ; Hariyama, M. ; Kameyama, M.

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1394-1406 [Periódico revisado por pares]

New York, NY: IEEE

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7
A SAR-Assisted Two-Stage Pipeline ADC
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A SAR-Assisted Two-Stage Pipeline ADC

Lee, C C ; Flynn, M P

IEEE journal of solid-state circuits, 2011-04, Vol.46 (4), p.859-869 [Periódico revisado por pares]

New York, NY: IEEE

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8
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Zhu, Ning ; Goh, Wang Ling ; Zhang, Weija ; Yeo, Kiat Seng ; Kong, Zhi Hui

IEEE transactions on very large scale integration (VLSI) systems, 2010-08, Vol.18 (8), p.1225-1229 [Periódico revisado por pares]

New York, NY: IEEE

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9
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories
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A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

Park, Ki-Tae ; Kang, Myounggon ; Kim, Doogon ; Hwang, Soon-Wook ; Choi, Byung Yong ; Lee, Yeong-Taek ; Kim, Changhyun ; Kim, Kinam

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.919-928 [Periódico revisado por pares]

New York, NY: IEEE

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10
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection
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A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection

Kyrkou, C ; Theocharides, T

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1034-1047 [Periódico revisado por pares]

New York, NY: IEEE

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