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Refinado por: Base de dados/Biblioteca: DOAJ Directory of Open Access Journals remover assunto: Exact Sciences And Technology remover Electronic Circuits remover Electric, Optical And Optoelectronic Circuits remover Design. Technologies. Operation Analysis. Testing remover
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FPGA accelerator for floating-point matrix multiplication
FPGA accelerator for floating-point matrix multiplication
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FPGA accelerator for floating-point matrix multiplication

JOVANOVIC, Z ; MILUTINOVIC, V

IET computers & digital techniques, 2012-07, Vol.6 (4), p.249-256 [Periódico revisado por pares]

Stevenage: Institution of Engineering and Technology

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2
VLSI architecture and chip for combined invisible robust and fragile watermarking
VLSI architecture and chip for combined invisible robust and fragile watermarking
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VLSI architecture and chip for combined invisible robust and fragile watermarking

MOHANTY, S. P ; KOUGIANOS, E ; RANGANATHAN, N

IET computers & digital techniques, 2007-09, Vol.1 (5), p.600-611 [Periódico revisado por pares]

Stevenage: Institution of Engineering and Technology

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3
VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor
VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor
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VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor

Hsia, Shih-Chang ; Chou, Ying-Chao

IET circuits, devices & systems, 2014-01, Vol.8 (1), p.10-18 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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4
Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays
Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays
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Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays

Amaricai, Alexandru ; Boncalo, Oana ; Gavriliu, Constantina-Elena

IET computers & digital techniques, 2014-07, Vol.8 (4), p.187-197 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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5
Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
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Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

WANG, J ; CHEN, Q. S ; LEE, C. H

IET computers & digital techniques, 2008-09, Vol.2 (5), p.386-400 [Periódico revisado por pares]

Stevenage: Institution of Engineering and Technology

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6
Reconfigurable baseband processing architecture for communication
Reconfigurable baseband processing architecture for communication
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Reconfigurable baseband processing architecture for communication

LU, W. Q ; ZHAO, S ; ZHOU, X. F ; REN, J. Y ; SOBELMAN, G. E

IET computers & digital techniques, 2011, Vol.5 (1), p.63-72 [Periódico revisado por pares]

Stevenage: Institution of Engineering and Technology

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7
Spur reducing architecture of frequency synthesiser using switched capacitors
Spur reducing architecture of frequency synthesiser using switched capacitors
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Spur reducing architecture of frequency synthesiser using switched capacitors

Mandal, Debashis ; Mandal, Pradip ; Bhattacharyya, Tarun Kanti

IET circuits, devices & systems, 2014-07, Vol.8 (4), p.237-245 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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8
Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation
Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation
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Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

Zhai, Xiaojun ; Bensaali, Faycal ; Ramalingam, Soodamani

IET circuits, devices & systems, 2013-03, Vol.7 (2), p.93-103 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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9
Field programmable gate array-based acceleration of shortest-path computation
Field programmable gate array-based acceleration of shortest-path computation
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Field programmable gate array-based acceleration of shortest-path computation

JAGADEESH, G. R ; SRIKANTHAN, T ; LIM, C. M

IET computers & digital techniques, 2011-07, Vol.5 (4), p.231-237 [Periódico revisado por pares]

Stevenage: Institution of Engineering and Technology

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10
Two-stage logarithmic converter with reduced memory requirements
Two-stage logarithmic converter with reduced memory requirements
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Two-stage logarithmic converter with reduced memory requirements

Chaudhary, Mandeep ; Lee, Peter

IET computers & digital techniques, 2014-01, Vol.8 (1), p.23-29 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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