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Refinado por: Base de dados/Biblioteca: ACM Digital Library remover assunto: Digital Circuits remover Design. Technologies. Operation Analysis. Testing remover
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1
First-order incremental block-based statistical timing analysis
First-order incremental block-based statistical timing analysis
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Ata de Congresso 		Adicionar ao Meu Espaço

First-order incremental block-based statistical timing analysis

Visweswariah, C. ; Ravindran, K. ; Kalafala, K. ; Walker, S. G. ; Narayan, S.

Proceedings of the 41st annual Design Automation Conference, 2004, p.331-336

New York, NY, USA: ACM

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2
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
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Artigo 		Adicionar ao Meu Espaço

A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors

GEBHART, Mark ; JOHNSON, Daniel R ; TARJAN, David ; KECKLER, Stephen W ; DALLY, William J ; LINDHOLM, Erik ; SKADRON, Kevin

ACM transactions on computer systems, 2012-04, Vol.30 (2), p.1-38 [Periódico revisado por pares]

New York, NY: Association for Computing Machinery

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3
An efficient algorithm for finding empty space for online FPGA placement
An efficient algorithm for finding empty space for online FPGA placement
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An efficient algorithm for finding empty space for online FPGA placement

Handa, Manish ; Vemuri, Ranga

Proceedings of the 41st annual Design Automation Conference, 2004, p.960-965

New York, NY, USA: ACM

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4
FPGA power reduction using configurable dual-Vdd
FPGA power reduction using configurable dual-Vdd
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FPGA power reduction using configurable dual-Vdd

Li, Fei ; Lin, Yan ; He, Lei

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.735-740

New York, NY, USA: ACM

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5
Automatic translation of software binaries onto FPGAs
Automatic translation of software binaries onto FPGAs
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Automatic translation of software binaries onto FPGAs

Mittal, Gaurav ; Zaretsky, David C. ; Tang, Xiaoyong ; Banerjee, P.

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.389-394

New York, NY, USA: ACM

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6
A new heuristic algorithm for reversible logic synthesis
A new heuristic algorithm for reversible logic synthesis
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A new heuristic algorithm for reversible logic synthesis

Kerntopf, Pawel

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.834-837

New York, NY, USA: ACM

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7
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
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An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design

Roy, Sanghamitra ; Banerjee, Prith

Proceedings of the 41st annual Design Automation Conference, 2004, p.484-487

New York, NY, USA: ACM

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8
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
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Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions

Antonelli, Dominic A. ; Chen, Danny Z. ; Dysart, Timothy J. ; Hu, Xiaobo S. ; Kahng, Andrew B. ; Kogge, Peter M. ; Murphy, Richard C. ; Niemier, Michael T.

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.363-368

New York, NY, USA: ACM

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9
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication
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A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Nakamura, Yuichi ; Hosokawa, Kouhei ; Kuroda, Ichiro ; Yoshikawa, Ko ; Yoshimura, Takeshi

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.299-304

New York, NY, USA: ACM

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10
Quantum logic synthesis by symbolic reachability analysis
Quantum logic synthesis by symbolic reachability analysis
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Quantum logic synthesis by symbolic reachability analysis

Hung, William N. N. ; Song, Xiaoyu ; Yang, Guowu ; Yang, Jin ; Perkowski, Marek

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.838-841

New York, NY, USA: ACM

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