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1
A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures
A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures
Material Type:
Artigo 		Adicionar ao Meu Espaço

A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures

Marcelo Antonio Pavanello João Antonio Martino 1959-

Journal de Physique IV Les Ulis Cedex v.8, p.45-48, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

2
Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K
Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K
Material Type:
Artigo 		Adicionar ao Meu Espaço

Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K

Marcelo Antonio Pavanello Aparecido Sirley Nicolett; João Antonio Martino 1959-

Journal de Physique IV Les Ulis Cedex v.8, p.49-52, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

3
A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures
A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures
Material Type:
Artigo 		Adicionar ao Meu Espaço

A new method to extract the effective trap density at the buried oxide underlying substrate interface in enhancement mode SOI MOSFETs at low temperatures

Marcelo Antonio Pavanello João Antonio Martino 1959-

Journal de Physique IV Les Ulis Cedex v.8, p.45-48, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

4
Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K
Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K
Material Type:
Artigo 		Adicionar ao Meu Espaço

Analysis of the substrate effect on enhancement mode SOInMOSFET effective channel length and series resistence extraction at 77K

Marcelo Antonio Pavanello Aparecido Sirley Nicolett; João Antonio Martino 1959-

Journal de Physique IV Les Ulis Cedex v.8, p.49-52, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

5
Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K
Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K
Material Type:
Artigo 		Adicionar ao Meu Espaço

Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K

Aparecido Sirley Nicolett João Antonio Martino 1959-; Eddy Simoen; Cor Claeys

Journal de Physique IV Les Ulis Cedex v.8, p.25-28, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

6
Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K
Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K
Material Type:
Artigo 		Adicionar ao Meu Espaço

Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K

Aparecido Sirley Nicolett João Antonio Martino 1959-; Eddy Simoen; Cor Claeys

Journal de Physique IV Les Ulis Cedex v.8, p.25-28, 1998

Les Ulis Cedex 1998

Item não circula. Consulte sua biblioteca.(Acessar)

7
Low temperature operation of graded-channel SOI nMOSFETs for analog applications
Low temperature operation of graded-channel SOI nMOSFETs for analog applications
Material Type:
Artigo 		Adicionar ao Meu Espaço

Low temperature operation of graded-channel SOI nMOSFETs for analog applications

Marcelo Antonio Pavanello Paula Ghedini Der Agopian; João Antonio Martino 1959-; Denis Flandre

Journal de Physique IV Paris: EDP Sciences, 2002 v.12, n.3, may 2002

Paris 2002

Item não circula. Consulte sua biblioteca.(Acessar)

8
Low temperature operation of graded-channel SOI nMOSFETs for analog applications
Low temperature operation of graded-channel SOI nMOSFETs for analog applications
Material Type:
Artigo 		Adicionar ao Meu Espaço

Low temperature operation of graded-channel SOI nMOSFETs for analog applications

Marcelo Antonio Pavanello Paula Ghedini Der Agopian; João Antonio Martino 1959-; Denis Flandre

Journal de Physique IV Paris: EDP Sciences, 2002 v.12, n.3, may 2002

Paris 2002

Item não circula. Consulte sua biblioteca.(Acessar)

9
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body
Material Type:
Artigo 		Adicionar ao Meu Espaço

Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body

Marcelo Antonio Pavanello João Antonio Martino 1959-; A Mercha; J.M Rafi; Eddy Simoen; Cor Claeys; H Van Meer; K De Meyer

Journal de Physique IV Paris: EDP Sciences, 2002 v.12, n.3, may 2002

Paris 2002

Item não circula. Consulte sua biblioteca.(Acessar)

10
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body
Material Type:
Artigo 		Adicionar ao Meu Espaço

Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body

Marcelo Antonio Pavanello João Antonio Martino 1959-; A Mercha; J.M Rafi; Eddy Simoen; Cor Claeys; H Van Meer; K De Meyer

Journal de Physique IV Paris: EDP Sciences, 2002 v.12, n.3, may 2002

Paris 2002

Item não circula. Consulte sua biblioteca.(Acessar)

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Deste Autor:

  1. Martino, J
  2. Pavanello, M
  3. Simoen, E
  4. Claeys, C
  5. Nicolett, A

Neste Assunto:

  1. Energia Elétrica
  2. Circuitos Integrados Mos
  3. Máquinas Elétricas
  4. Equipamentos Elétricos

  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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