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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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2
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2004-06, Vol.12 (6), p.573-589 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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3
Partitioning and pipelining for performance-constrained hardware/software systems
Partitioning and pipelining for performance-constrained hardware/software systems
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Partitioning and pipelining for performance-constrained hardware/software systems

Bakshi, S. ; Gajski, D.D.

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.419-432 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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4
Efficient timing closure without timing driven placement and routing
Efficient timing closure without timing driven placement and routing
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Efficient timing closure without timing driven placement and routing

Vujkovic, Miodrag ; Wadkins, David ; Swartz, Bill ; Sechen, Carl

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.268-273

New York, NY, USA: ACM

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5
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
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Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Ricci, Andrea ; De Munari, Ilaria ; Ciampolini, Paolo

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, p.315-322

IEEE

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6
Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization
Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization
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Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization

Ibarra-Manzano, M.A. ; Almanza-Ojeda, D.-L. ; Devy, M. ; Boizard, J.-L. ; Fourniols, J.-Y.

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, p.799-805

IEEE

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7
Teaching digital HW-design by implementing a complete MP3 decoder
Teaching digital HW-design by implementing a complete MP3 decoder
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Teaching digital HW-design by implementing a complete MP3 decoder

Hedberg, H. ; Lenart, T. ; Svensson, H. ; Nilsson, P. ; Owall, V.

IEEE International Conference on Microelectronic Systems Education (MSE), 2003,Anaheim, CA, United States,2003-06-01 - 2003-06-02, 2003, p.31-32

IEEE

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8
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
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Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips

Roy, Sudip ; Bhattacharya, Bhargab B ; Chakrabarty, Krishnendu

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-11, Vol.29 (11), p.1696-1708 [Periódico revisado por pares]

New York: IEEE

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9
Obfuscating DSP Circuits via High-Level Transformations
Obfuscating DSP Circuits via High-Level Transformations
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Obfuscating DSP Circuits via High-Level Transformations

Yingjie Lao ; Parhi, Keshab K.

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.819-830 [Periódico revisado por pares]

IEEE

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10
Modular Design of High-Throughput, Low-Latency Sorting Units
Modular Design of High-Throughput, Low-Latency Sorting Units
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Modular Design of High-Throughput, Low-Latency Sorting Units

Farmahini-Farahani, A. ; Duwe, H. J. ; Schulte, M. J. ; Compton, K.

IEEE transactions on computers, 2013-07, Vol.62 (7), p.1389-1402 [Periódico revisado por pares]

New York: IEEE

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