Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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Material Type: Artigo
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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraintsChabini, N. ; Wolf, W.IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126 [Periódico revisado por pares]Piscataway, NJ: IEEETexto completo disponível |
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Material Type: Artigo
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Partitioning and pipelining for performance-constrained hardware/software systemsBakshi, S. ; Gajski, D.D.IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.419-432 [Periódico revisado por pares]Piscataway, NJ: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Efficient timing closure without timing driven placement and routingVujkovic, Miodrag ; Wadkins, David ; Swartz, Bill ; Sechen, CarlAnnual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.268-273New York, NY, USA: ACMTexto completo disponível |
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Material Type: Artigo
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An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realizationGUO, Jiun-In ; JU, Rei-Chin ; CHEN, Jia-WeiIEEE transactions on circuits and systems for video technology, 2004-04, Vol.14 (4), p.416-428 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Design of digital general-purpose PSO processorMalekara, Asal ; Khalilzadegan, Amin ; Khoei, Abdollah2016 24th Iranian Conference on Electrical Engineering (ICEE), 2016, p.1377-1382IEEESem texto completo |
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Material Type: Ata de Congresso
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Hardware architecture design and mapping of 'Fast Inverse Square Root' algorithmZafar, Saad ; Adapa, Raviteja2014 International Conference on Advances in Electrical Engineering (ICAEE), 2014, p.1-4IEEESem texto completo |
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Material Type: Ata de Congresso
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Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear PairingsChavez Corona, Cuautemoc ; Moreno, E. F. ; Henriquez, F. R.2011 International Conference on Reconfigurable Computing and FPGAs, 2011, p.229-234IEEETexto completo disponível |
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Material Type: Ata de Congresso
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DNA tiling for digital evolvable hardwareHaddow, Pauline C. ; Gautam, Vinay Kumar2013 IEEE International Conference on Evolvable Systems (ICES), 2013, p.104-111IEEETexto completo disponível |
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Material Type: Artigo
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Hardware efficient digital filter design by multimode mean field annealingPersson, P. ; Nordebo, S. ; Claesson, I.IEEE signal processing letters, 2001-07, Vol.8 (7), p.193-195 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Integrated software-hardware design for ultra-low power infrastructure monitoringWu, Jingxian ; Smith, Scott C.2009 12th International IEEE Conference on Intelligent Transportation Systems, 2009, p.1-8IEEETexto completo disponível |