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Obfuscating DSP Circuits via High-Level Transformations
Obfuscating DSP Circuits via High-Level Transformations
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Obfuscating DSP Circuits via High-Level Transformations

Yingjie Lao ; Parhi, Keshab K.

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.819-830 [Periódico revisado por pares]

IEEE

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2
Modular Design of High-Throughput, Low-Latency Sorting Units
Modular Design of High-Throughput, Low-Latency Sorting Units
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Modular Design of High-Throughput, Low-Latency Sorting Units

Farmahini-Farahani, A. ; Duwe, H. J. ; Schulte, M. J. ; Compton, K.

IEEE transactions on computers, 2013-07, Vol.62 (7), p.1389-1402 [Periódico revisado por pares]

New York: IEEE

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3
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
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Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

Narayanamoorthy, Srinivasan ; Moghaddam, Hadi Asghari ; Zhenhong Liu ; Taejoon Park ; Nam Sung Kim

IEEE transactions on very large scale integration (VLSI) systems, 2015-06, Vol.23 (6), p.1180-1184 [Periódico revisado por pares]

IEEE

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4
Evaluation of Large Integer Multiplication Methods on Hardware
Evaluation of Large Integer Multiplication Methods on Hardware
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Evaluation of Large Integer Multiplication Methods on Hardware

Rafferty, Ciara ; O'Neill, Maire ; Hanley, Neil

IEEE transactions on computers, 2017-08, Vol.66 (8), p.1369-1382 [Periódico revisado por pares]

New York: IEEE

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5
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
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Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing

Guan, Xuan ; Fei, Yunsi ; Lin, Hai

IEEE transactions on very large scale integration (VLSI) systems, 2012-03, Vol.20 (3), p.551-563 [Periódico revisado por pares]

New York, NY: IEEE

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6
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks
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WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks

Yang, Chen ; Meng, Yishuo ; Xi, Jiawei ; Xiang, Siwei ; Wang, Jianfei ; Mei, Kuizhi

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.164-177 [Periódico revisado por pares]

IEEE

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7
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier
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High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier

Chen, Jiajia ; Chang, Chip-Hong

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-12, Vol.28 (12), p.1844-1856 [Periódico revisado por pares]

New York: IEEE

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8
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction
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A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction

Ding, Jiatao ; Chen, Jiajia ; Chang, Chip-Hong

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-10, Vol.35 (10), p.1605-1617 [Periódico revisado por pares]

New York: IEEE

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9
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications
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Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications

Aksoy, L. ; da Costa, E. ; Flores, P. ; Monteiro, J.

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-06, Vol.27 (6), p.1013-1026 [Periódico revisado por pares]

New York: IEEE

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10
DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures
DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures
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DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures

Coelho, Diego F. G. ; Cintra, Renato J. ; Rajapaksha, Nilanka ; Madanayake, Arjuna ; Dimitrov, Vassil S.

IEEE transactions on computers, 2017-08, Vol.66 (8), p.1442-1448 [Periódico revisado por pares]

New York: IEEE

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