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A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits
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A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Moaiyeri, Mohammad Hossein ; Mirzaee, Reza Faghih ; Doostaregan, Akbar ; Navi, Keivan ; Hashemipour, Omid

IET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181 [Periódico revisado por pares]

Stevenage: The Institution of Engineering and Technology

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Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source
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Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Azimi, Nooshin ; Mirzaee, Reza Faghih ; Navi, Keivan ; Rahmani, Amir Masoud

IET computers & digital techniques, 2020-07, Vol.14 (4), p.166-175 [Periódico revisado por pares]

The Institution of Engineering and Technology

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3
In memory computation using quantum-dot cellular automata
In memory computation using quantum-dot cellular automata
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In memory computation using quantum-dot cellular automata

Goswami, Mrinal ; Pal, Jayanta ; Roy Choudhury, Mayukh ; Chougule, Pritam P ; Sen, Bibhash

IET computers & digital techniques, 2020-11, Vol.14 (6), p.336-343 [Periódico revisado por pares]

The Institution of Engineering and Technology

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Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays
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Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

Yang, Zongxian ; Pan, Kangqiang ; Zhou, Norman Y. ; Wei, Lan

IEEE journal on exploratory solid-state computational devices and circuits, 2022-12, Vol.8 (2), p.84-92 [Periódico revisado por pares]

Piscataway: IEEE

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5
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis
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Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis

Shang, Liuting ; Naeemi, Azad ; Pan, Chenyun

IEEE open journal of the Computer Society, 2023-01, Vol.4, p.1-12 [Periódico revisado por pares]

New York: IEEE

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RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
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RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Coluccio, Andrea ; Ieva, Antonia ; Riente, Fabrizio ; Roch, Massimo Ruo ; Ottavi, Marco ; Vacca, Marco

Electronics (Basel), 2022-10, Vol.11 (19), p.2990 [Periódico revisado por pares]

Basel: MDPI AG

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7
Analysis of Network Slicing for Management of 5G Networks Using Machine Learning Techniques
Analysis of Network Slicing for Management of 5G Networks Using Machine Learning Techniques
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Analysis of Network Slicing for Management of 5G Networks Using Machine Learning Techniques

Singh, Randeep ; Mehbodniya, Abolfazl ; Webber, Julian L. ; Dadheech, Pankaj ; Pavithra, G. ; Alzaidi, Mohammed S. ; Akwafo, Reynah Rajakani, Kalidoss ; Kalidoss Rajakani

Wireless communications and mobile computing, 2022-06, Vol.2022, p.1-10 [Periódico revisado por pares]

Oxford: Hindawi

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8
Verification of serialising instructions for security against transient execution attacks
Verification of serialising instructions for security against transient execution attacks
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Verification of serialising instructions for security against transient execution attacks

Ponugoti, Kushal K. ; Srinivasan, Sudarshan K. ; Mathure, Nimish

IET computers & digital techniques, 2023-07, Vol.17 (3-4), p.127-140 [Periódico revisado por pares]

Hindawi-IET

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9
Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices
Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices
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Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Chakraborty, Anindita ; Maurya, Vivek ; Prasad, Sneha ; Gupta, Suryansh ; Chakraborty, Rajat Subhra ; Rahaman, Hafizur

IET computers & digital techniques, 2021-03, Vol.15 (2), p.112-124 [Periódico revisado por pares]

Hindawi-IET

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10
Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications
Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications
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Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications

Hossain, Md Selim ; Saeedi, Ehsan ; Kong, Yinan Choo, Kim-Kwang Raymond

PloS one, 2017-05, Vol.12 (5), p.e0176214-e0176214 [Periódico revisado por pares]

United States: Public Library of Science

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