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Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
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Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network

Wang, Maolin ; Lee, Kelvin C. M. ; Chung, Bob M. F. ; Bogaraju, Sharatchandra Varma ; Ng, Ho-Cheung ; Wong, Justin S. J. ; Shum, Ho Cheung ; Tsia, Kevin K. ; So, Hayden Kwok-Hay

IEEE transaction on neural networks and learning systems, 2022-07, Vol.PP (7), p.1-14

United States: IEEE

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FPGA implementation of hardware accelerated RTOS based on real-time event handling
FPGA implementation of hardware accelerated RTOS based on real-time event handling
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FPGA implementation of hardware accelerated RTOS based on real-time event handling

Zagan, Ionel ; Găitan, Vasile Gheorghiță

The Journal of supercomputing, 2023-07, Vol.79 (11), p.12441-12471 [Periódico revisado por pares]

New York: Springer US

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3
A new flexible coupler for earth system modeling developed for CCSM4 and CESM1
A new flexible coupler for earth system modeling developed for CCSM4 and CESM1
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A new flexible coupler for earth system modeling developed for CCSM4 and CESM1

Craig, Anthony P. ; Vertenstein, Mariana ; Jacob, Robert

International Journal of High Performance Computing Applications, 2012-02, Vol.26 (1), p.31-42 [Periódico revisado por pares]

London, England: SAGE Publications

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4
Towards cardiac intervention assistance: hardware-aware neural architecture exploration for real-time 3D cardiac cine MRI segmentation
Towards cardiac intervention assistance: hardware-aware neural architecture exploration for real-time 3D cardiac cine MRI segmentation
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Towards cardiac intervention assistance: hardware-aware neural architecture exploration for real-time 3D cardiac cine MRI segmentation

Zeng, Dewen ; Jiang, Weiwen ; Wang, Tianchen ; Xu, Xiaowei ; Yuan, Haiyun ; Huang, Meiping ; Zhuang, Jian ; Hu, Jingtong ; Shi, Yiyu

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8

New York, NY, USA: ACM

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5
Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems
Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems
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Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems

Coppock, Patrick H. ; Yacoub, Momen K. ; Qin, Bruce L. ; Daftardar, Alhad J. ; Tolaymat, Zayd ; Mooney, Vincent J.

Microprocessors and microsystems, 2020-11, Vol.79, p.103270, Article 103270 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models
Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models
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Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models

Bir, Parth ; Karatangi, Shylaja Vinaykumar ; Rai, Amrita

The Journal of supercomputing, 2020-09, Vol.76 (9), p.7394-7415 [Periódico revisado por pares]

New York: Springer US

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7
SDPA: Toward a Stateful Data Plane in Software-Defined Networking
SDPA: Toward a Stateful Data Plane in Software-Defined Networking
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SDPA: Toward a Stateful Data Plane in Software-Defined Networking

Sun, Chen ; Bi, Jun ; Chen, Haoxian ; Hu, Hongxin ; Zheng, Zhilong ; Zhu, Shuyong ; Wu, Chenghui

IEEE/ACM transactions on networking, 2017-12, Vol.25 (6), p.3294-3308 [Periódico revisado por pares]

New York: IEEE

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8
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
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A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension

Patsidis, Karyofyllis ; Konstantinou, Dimitris ; Nicopoulos, Chrysostomos ; Dimitrakopoulos, Giorgos

Microprocessors and microsystems, 2018-09, Vol.61, p.1-10 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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9
Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation
Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation
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Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation

Ez-ziymy, Siham ; Hatim, Anas ; Hammia, Slama

Multimedia tools and applications, 2024-03, Vol.83 (10), p.30937-30961 [Periódico revisado por pares]

New York: Springer US

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10
Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures
Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures
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Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Roux, Baptiste ; Gautier, Matthieu ; Sentieys, Olivier ; Delahaye, Jean-Philippe

Microprocessors and microsystems, 2020-09, Vol.77, p.103138-12, Article 103138 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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