Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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Material Type: Artigo
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Scalability of Broadcast Performance in Wireless Network-on-ChipAbadal, Sergi ; Mestres, Albert ; Nemirovsky, Mario ; Heekwan Lee ; Gonzalez, Antonio ; Alarcon, Eduard ; Cabellos-Aparicio, AlbertIEEE transactions on parallel and distributed systems, 2016-12, Vol.27 (12), p.3631-3645 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Reducing Cache Coherence Traffic with a NUMA-Aware Runtime ApproachCaheny, Paul ; Alvarez, Lluc ; Derradji, Said ; Valero, Mateo ; Moreto, Miquel ; Casas, MarcIEEE transactions on parallel and distributed systems, 2018-05, Vol.29 (5), p.1174-1187 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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3 |
Material Type: Ata de Congresso
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Performance analysis and optimization of the FFTXlib on the Intel knights landing architectureWagner, Michael ; López, Victor ; Morillo, Julian ; Cavazzoni, Carlo ; Affinito, Fabio ; Gimenez, Judit ; Labarta Mancho, Jesús JoséInstitute of Electrical and Electronics Engineers (IEEE) 2017Texto completo disponível |
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Material Type: Artigo
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Enlarging Instruction StreamsDesmet, L. ; Verbaeten, P. ; Joosen, W. ; Piessens, F.IEEE transactions on computers, 2007-10, Vol.56 (10), p.1342-1357 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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Software-Controlled Priority Characterization of POWER5 ProcessorBoneti, Carlos ; Cazorla, Francisco J. ; Gioiosa, Roberto ; Buyuktosunoglu, Alper ; Cher, Chen-Yong ; Valero, Mateo2008 International Symposium on Computer Architecture, 2008, p.415-426Washington, DC, USA: IEEE Computer SocietyTexto completo disponível |
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Material Type: Ata de Congresso
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A distributed processor state management architecture for large-window processorsGonzalez, Isidro ; Galluzzi, Marco ; Veidenbaum, Alex ; Ramirez, Marco A. ; Cristal, Adrian ; Valero, Mateo2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008, p.11-22Washington, DC, USA: IEEE Computer SocietyTexto completo disponível |
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7 |
Material Type: Ata de Congresso
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A Two-Level Load/Store Queue Based on Execution LocalityPericàs, Miquel ; Cristal, Adrian ; Cazorla, Francisco J. ; González, Ruben ; Veidenbaum, Alex ; Jiménez, Daniel A. ; Valero, Mateo2008 International Symposium on Computer Architecture, 2008, p.25-36Washington, DC, USA: IEEE Computer SocietyTexto completo disponível |
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8 |
Material Type: Ata de Congresso
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Value prediction for speculative multithreaded architecturesMarcuello, P. ; Tubella, J. ; Gonzalez, A.MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.230-236IEEETexto completo disponível |
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9 |
Material Type: Ata de Congresso
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Exploiting a new level of DLP in multimedia applicationsCorbal, J. ; Valero, M. ; Espasa, R.MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.72-79IEEETexto completo disponível |
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10 |
Material Type: Artigo
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A Bi-layered Parallel Training Architecture for Large-Scale Convolutional Neural NetworksChen, Jianguo ; Li, Kenli ; Bilal, Kashif ; Zhou, Xu ; Li, Keqin ; Yu, Philip S.IEEE transactions on parallel and distributed systems, 2019-05, Vol.30 (5), p.965-976 [Periódico revisado por pares]New York: IEEETexto completo disponível |