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Refinado por: assunto: Cryptography remover assunto: Hardware remover Fpga remover
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1
High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber
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High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber

Dang, Viet Ba ; Mohajerani, Kamyar ; Gaj, Kris

IEEE transactions on computers, 2023-02, Vol.72 (2), p.306-320 [Periódico revisado por pares]

IEEE

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Instruction-Set Accelerated Implementation of CRYSTALS-Kyber
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Instruction-Set Accelerated Implementation of CRYSTALS-Kyber

Bisheh-Niasar, Mojtaba ; Azarderakhsh, Reza ; Mozaffari-Kermani, Mehran

IEEE transactions on circuits and systems. I, Regular papers, 2021-11, Vol.68 (11), p.4648-4659 [Periódico revisado por pares]

New York: IEEE

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3
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
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Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme

Mert, Ahmet Can ; Ozturk, Erdinc ; Savas, Erkay

IEEE transactions on very large scale integration (VLSI) systems, 2020-02, Vol.28 (2), p.353-362 [Periódico revisado por pares]

New York: IEEE

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4
KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture
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KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture

Wong, Zheng-Yan ; Wong, Denis C.-K. ; Lee, Wai-Kong ; Mok, Kai-Ming ; Yap, Wun-She ; Khalid, Ayesha

IEEE transactions on computers, 2023-07, Vol.72 (7), p.1830-1842 [Periódico revisado por pares]

IEEE

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5
High Performance Modular Multiplication for SIDH
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High Performance Modular Multiplication for SIDH

Liu, Weiqiang ; Ni, Ziying ; Ni, Jian ; Rafferty, Ciara ; O'Neill, Maire

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.3118-3122 [Periódico revisado por pares]

New York: IEEE

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6
High-performance elliptic curve cryptography processor over NIST prime fields
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High-performance elliptic curve cryptography processor over NIST prime fields

Hossain, Md Selim ; Kong, Yinan ; Saeedi, Ehsan ; Vayalil, Niras C

IET computers & digital techniques, 2017-01, Vol.11 (1), p.33-42 [Periódico revisado por pares]

The Institution of Engineering and Technology

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7
A reconfigurable and compact subpipelined architecture for AES encryption and decryption
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A reconfigurable and compact subpipelined architecture for AES encryption and decryption

Li, Ke ; Li, Hua ; Mund, Graeme

EURASIP journal on advances in signal processing, 2023-01, Vol.2023 (1), p.5-21, Article 5 [Periódico revisado por pares]

Cham: Springer International Publishing

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8
Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption
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Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

Xiaolin Cao ; Moore, Ciara ; O'Neill, Maire ; O'Sullivan, Elizabeth ; Hanley, Neil

IEEE transactions on computers, 2016-09, Vol.65 (9), p.2794-2806 [Periódico revisado por pares]

New York: IEEE

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9
A new multi-scroll Chua’s circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application
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A new multi-scroll Chua’s circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application

Yu, Fei ; Shen, Hui ; Zhang, Zinan ; Huang, Yuanyuan ; Cai, Shuo ; Du, Sichun

Integration (Amsterdam), 2021-11, Vol.81, p.71-83 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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10
High throughput unified architecture of LEA algorithm for image encryption
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High throughput unified architecture of LEA algorithm for image encryption

Mishra, Zeesha ; Nath, Pallab Kumar ; Acharya, Bibhudendra

Microprocessors and microsystems, 2020-10, Vol.78, p.103214, Article 103214 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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