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1
K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture
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K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

An, Fengwei ; Mihara, Keisuke ; Yamasaki, Shogo ; Chen, Lei ; Mattausch, Hans Jurgen

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(4), 70, pp.405-414

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High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement
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High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

Byun, Wooseok ; Kim, Hyeji ; Kim, Ji-Hoon

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14(4), 58, pp.407-418

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Efficient Reconfigurable Architecture to Accelerate Descriptor Extraction in SURF Algorithm
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Efficient Reconfigurable Architecture to Accelerate Descriptor Extraction in SURF Algorithm

Kim, Yoonjin ; Jung, Haelim

Journal of semiconductor technology and science, 2018, Vol.18 (3), p.396-401

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Scalable Application Mapping for SIMD Reconfigurable Architecture
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Scalable Application Mapping for SIMD Reconfigurable Architecture

Kim, Yongjoo ; Lee, Jongeun ; Lee, Jinyong ; Paek, Yunheung

Journal of semiconductor technology and science, 2015, Vol.15 (6), p.634-646

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5
Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor
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Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

Nguyen, Tuy Tan ; Lee, Hanho

Journal of semiconductor technology and science, 2016, Vol.16 (1), p.118-125

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6
A Memory-efficient Hand Segmentation Architecture for Hand Gesture Recognition in Low-power Mobile Devices
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A Memory-efficient Hand Segmentation Architecture for Hand Gesture Recognition in Low-power Mobile Devices

Choi, Sungpill ; Park, Seongwook ; Yoo, Hoi-Jun

Journal of semiconductor technology and science, 2017, Vol.17 (3), p.473-482

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7
Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture
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Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture

Kim, Yoonjin ; Sohn, Seungyeon

Journal of semiconductor technology and science, 2015, Vol.15 (2), p.307-311

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8
Performance Analysis of Shared Buffer Router Architecture for Low Power Applications
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Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

Deivakani, M ; Shanthi, D

Journal of semiconductor technology and science, 2016, Vol.16 (6), p.736-744

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9
Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications
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Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

Jung, Boseok ; Kim, Taesung ; Lee, Hanho

Journal of semiconductor technology and science, 2016, Vol.16 (4), p.488-496

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Energy-Efficient and High Performance CGRA-based Multi-Core Architecture
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Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Kim, Yoonjin ; Kim, Heesun

Journal of semiconductor technology and science, 2014, Vol.14 (3), p.284-299

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