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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover assunto: Software remover
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Hardware/Software Co-Exploration of Neural Architectures
Hardware/Software Co-Exploration of Neural Architectures
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Hardware/Software Co-Exploration of Neural Architectures

Jiang, Weiwen ; Yang, Lei ; Sha, Edwin Hsing-Mean ; Zhuge, Qingfeng ; Gu, Shouzhen ; Dasgupta, Sakyasingha ; Shi, Yiyu ; Hu, Jingtong

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815 [Periódico revisado por pares]

New York: IEEE

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2
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
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Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment

Sarkar, Ardhendu ; Ghosh, Surajeet

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2365-2378 [Periódico revisado por pares]

New York: IEEE

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3
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
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Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

Zhang, Chen ; Sun, Guangyu ; Fang, Zhenman ; Zhou, Peipei ; Pan, Peichen ; Cong, Jason

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-11, Vol.38 (11), p.2072-2085 [Periódico revisado por pares]

New York: IEEE

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4
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification
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ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Grandmaison, Arnaud de ; Heydemann, Karine ; Meunier, Quentin L.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.3733-3744 [Periódico revisado por pares]

New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)

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5
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory
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GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory

Chen, Jiaxian ; Lin, Yiquan ; Sun, Kaoyi ; Chen, Jiexin ; Ma, Chenlin ; Mao, Rui ; Wang, Yi

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.3579-3590 [Periódico revisado por pares]

New York: IEEE

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6
ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices
ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices
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ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices

Asokan, N. ; Nyman, Thomas ; Rattanavipanon, Norrathep ; Sadeghi, Ahmad-Reza ; Tsudik, Gene

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2290-2300 [Periódico revisado por pares]

New York: IEEE

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7
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems
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Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems

Pala, Davide ; Miro-Panades, Ivan ; Sentieys, Olivier

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1559-1572 [Periódico revisado por pares]

New York: IEEE

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8
Risk-5: Controlled Approximations for RISC-V
Risk-5: Controlled Approximations for RISC-V
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Risk-5: Controlled Approximations for RISC-V

Felzmann, Isaias ; Filho, Joao Fabricio ; Wanner, Lucas

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.4052-4063 [Periódico revisado por pares]

New York: IEEE

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9
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Cong, Jason ; Li, Peng ; Xiao, Bingjun ; Zhang, Peng

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-03, Vol.35 (3), p.407-418 [Periódico revisado por pares]

New York: IEEE

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10
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search
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Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search

Zhou, Xiangzhen ; Li, Sanjiang ; Feng, Yuan

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4683-4694 [Periódico revisado por pares]

New York: IEEE

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