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1
Fundamental Limits on the Precision of In-memory Architectures
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Fundamental Limits on the Precision of In-memory Architectures

Gonugondla, Sujan K. ; Sakr, Charbel ; Dbouk, Hassan ; Shanbhag, Naresh R.

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

Association on Computer Machinery

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Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
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Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems

Mutlu, Onur ; Moscibroda, Thomas

2008 International Symposium on Computer Architecture, 2008, p.63-74

IEEE Computer Society

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3
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
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Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance

Cho, Sangyeun ; Lee, Hyunjin

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.347-357

ACM

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4
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
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Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

Seshadri, Vivek ; Lee, Donghyuk ; Mullins, Thomas ; Hassan, Hasan ; Boroumand, Amirali ; Kim, Jeremie ; Kozuch, Michael ; Mutlu, Onur ; Gibbons, Phillip ; Mowry, Todd

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.273-287

ACM

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5
3D-Stacked Memory Architectures for Multi-core Processors
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3D-Stacked Memory Architectures for Multi-core Processors

Loh, Gabriel

2008 International Symposium on Computer Architecture, 2008, p.453-464

IEEE Computer Society

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6
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
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Self-Optimizing Memory Controllers: A Reinforcement Learning Approach

Ipek, Engin ; Mutlu, Onur ; Martínez, José ; Caruana, Rich

2008 International Symposium on Computer Architecture, 2008, p.39-50

IEEE Computer Society

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7
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications
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On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications

Chen, Hung-Ming ; Hu, Chia-Lin ; Chang, Kang-Yu ; Kuster, Alexandra ; Lin, Yu-Hsien ; Kuo, Po-Shen ; Chao, Wei-Tung ; Lai, Bo-Cheng ; Liu, Chien-Nan ; Jou, Shyh-Jye

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-8

Association on Computer Machinery

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8
Improving NAND Flash Based Disk Caches
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Improving NAND Flash Based Disk Caches

Kgil, Taeho ; Roberts, David ; Mudge, Trevor

2008 International Symposium on Computer Architecture, 2008, p.327-338

IEEE Computer Society

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9
A software memory partition approach for eliminating bank-level interference in multicore systems
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A software memory partition approach for eliminating bank-level interference in multicore systems

Liu, Lei ; Cui, Zehan ; Xing, Mingjie ; Bao, Yungang ; Chen, Mingyu ; Wu, Chengyong

2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012, p.367-376

ACM

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10
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
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Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

Meswani, Mitesh R. ; Blagodurov, Sergey ; Roberts, David ; Slice, John ; Ignatowski, Mike ; Loh, Gabriel H.

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), 2015, p.126-136

IEEE

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