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Refinado por: Nome da Publicação: Ieice Transactions On Fundamentals Of Electronics, Communications And Computer Sciences remover
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11
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
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Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent

TAKABE, Satoshi ; WADAYAMA, Tadashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/08/01, Vol.E105.A(8), pp.1110-1120 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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12
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
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Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework

YOSHIYA, Eiji ; NAKANISHI, Tomoya ; ISSHIKI, Tsuyoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/07/01, Vol.E105.A(7), pp.1061-1069 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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13
Prime-factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
Prime-factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
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Prime-factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes

CHANG, Yanyan ; ZHANG, Wei ; WANG, Hao ; SHI, Lina ; LIU, Yanyan

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2023, pp.2023EAL2044 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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14
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
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A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution

NANNIPIERI, Pietro ; DAVALLE, Daniele ; FANUCCI, Luca

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/07/01, Vol.E101.A(7), pp.1120-1122 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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15
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation

HATTORI, Naoki ; SHIOMI, Jun ; MASUDA, Yutaka ; ISHIHARA, Tohru ; SHINYA, Akihiko ; NOTOMI, Masaya

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/11/01, Vol.E104.A(11), pp.1477-1487 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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16
Scalable and Parameterized Architecture for Efficient Stream Mining
Scalable and Parameterized Architecture for Efficient Stream Mining
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Scalable and Parameterized Architecture for Efficient Stream Mining

ZHANG, Li ; LI, Dawei ; ZOU, Xuecheng ; HU, Yu ; XU, Xiaowei

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/01/01, Vol.E101.A(1), pp.219-231 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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17
Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
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Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher

Yli-Maeyry, Ville ; Homma, Naofumi ; Aoki, Takafumi

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (1), p.149-157 [Periódico revisado por pares]

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18
A Cell Probe-Based Method for Vehicle Speed Estimation
A Cell Probe-Based Method for Vehicle Speed Estimation
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A Cell Probe-Based Method for Vehicle Speed Estimation

CHEN, Chi-Hua

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2020/01/01, Vol.E103.A(1), pp.265-267 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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19
An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement
An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement
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An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement

MATSUO, Atsushi ; HATTORI, Wakaki ; YAMASHITA, Shigeru

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022, pp.2022EAP1050 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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20
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture
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A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture

XING, Qianjian ; MA, Zhenguo ; YU, Feng

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2017/06/01, Vol.E100.A(6), pp.1333-1337 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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