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Using global code motions to improve the quality of results for high-level synthesis
Using global code motions to improve the quality of results for high-level synthesis
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Using global code motions to improve the quality of results for high-level synthesis

Gupta, S. ; Savoiu, N. ; Dutt, N. ; Gupta, R. ; Nicolau, A.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-02, Vol.23 (2), p.302-312 [Periódico revisado por pares]

New York: IEEE

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2
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level
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Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level

Ara, K. ; Suzuki, K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-08, Vol.24 (8), p.1234-1240 [Periódico revisado por pares]

New York: IEEE

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3
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation
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Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation

Devadas, S. ; Keutzer, K. ; White, J.

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-03, Vol.11 (3), p.373-383 [Periódico revisado por pares]

PISCATAWAY: IEEE

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4
SIERA: a unified framework for rapid-prototyping of system-level hardware and software
SIERA: a unified framework for rapid-prototyping of system-level hardware and software
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SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Srivastava, M. ; Brodersen, R.W.

IEEE transactions on computer-aided design of integrated circuits and systems, 1995, Vol.14 (6), p.676-693 [Periódico revisado por pares]

New York, NY: IEEE

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5
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
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Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams

Lin, B. ; Devadas, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-08, Vol.14 (8), p.974-985 [Periódico revisado por pares]

New York, NY: IEEE

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