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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover assunto: Algorithms remover
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SCANN: Synthesis of Compact and Accurate Neural Networks
SCANN: Synthesis of Compact and Accurate Neural Networks
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SCANN: Synthesis of Compact and Accurate Neural Networks

Hassantabar, Shayan ; Wang, Zeyu ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025 [Periódico revisado por pares]

New York: IEEE

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2
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Chen, Pai-Yu ; Peng, Xiaochen ; Yu, Shimeng

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080 [Periódico revisado por pares]

New York: IEEE

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3
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training
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DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training

Peng, Xiaochen ; Huang, Shanshi ; Jiang, Hongwu ; Lu, Anni ; Yu, Shimeng

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-11, Vol.40 (11), p.2306-2319 [Periódico revisado por pares]

New York: IEEE

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4
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing
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GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing

Dai, Guohao ; Huang, Tianhao ; Chi, Yuze ; Zhao, Jishen ; Sun, Guangyu ; Liu, Yongpan ; Wang, Yu ; Xie, Yuan ; Yang, Huazhong

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-04, Vol.38 (4), p.640-653 [Periódico revisado por pares]

New York: IEEE

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5
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture
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Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture

Chang, Kuan-Yu ; Lee, Chun-Yi

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3373-3386 [Periódico revisado por pares]

New York: IEEE

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6
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits
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Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits

Yan, Jin-Tai

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-04, Vol.41 (4), p.1090-1102 [Periódico revisado por pares]

New York: IEEE

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7
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
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DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators

Xing, Yu ; Liang, Shuang ; Sui, Lingzhi ; Jia, Xijie ; Qiu, Jiantao ; Liu, Xin ; Wang, Yushun ; Shan, Yi ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2668-2681 [Periódico revisado por pares]

New York: IEEE

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8
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
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An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures

Wu, Chen ; Deng, Chenchen ; Liu, Leibo ; Han, Jie ; Chen, Jiqiang ; Yin, Shouyi ; Wei, Shaojun

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-08, Vol.34 (8), p.1264-1277 [Periódico revisado por pares]

New York: IEEE

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9
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms
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Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms

Liu, Leibo ; Wang, Bo ; Deng, Chenchen ; Zhu, Min ; Yin, Shouyi ; Wei, Shaojun

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3081-3094 [Periódico revisado por pares]

New York: IEEE

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10
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice
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Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Pelcat, Maxime ; Mercat, Alexandre ; Desnos, Karol ; Maggiani, Luca ; Liu, Yanzhou ; Heulot, Julien ; Nezan, Jean-Francois ; Hamidouche, Wassim ; Menard, Daniel ; Bhattacharyya, Shuvra S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-10, Vol.37 (10), p.2050-2063 [Periódico revisado por pares]

New York: IEEE

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