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0.8 μm cmos implementation of weighted-order statistic image filter based on cellular neural network architecture
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Artigo
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0.8 μm cmos implementation of weighted-order statistic image filter based on cellular neural network architecture

Kowalski, J

IEEE transactions on neural networks, 2003-09, Vol.14 (5), p.1366-1374

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2
1-D continuous non-minimum phase retrieval using the wavelet transform
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Ata de Congresso
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1-D continuous non-minimum phase retrieval using the wavelet transform

Bell, A.E. ; Yagle, A.E.

Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181), 1998, Vol.3, p.1641-1644 vol.3

IEEE

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3
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches
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100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches

Wang, Chua-Chin ; Lu, Shao-Wei

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, p.98-101

IEEE

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4
1.8 GHz CMOS LNA with on-chip DC-coupling for a subsampling direct conversion front-end
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1.8 GHz CMOS LNA with on-chip DC-coupling for a subsampling direct conversion front-end

Parssinen, A. ; Lindfors, S. ; Ryynanen, J. ; Long, S.I. ; Halonen, K.

1998 IEEE International Symposium on Circuits and Systems (ISCAS), 1998, Vol.2, p.73-76 vol.2

IEEE

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5
A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation
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A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation

Han, Donghyeon ; Im, Dongseok ; Park, Gwangtae ; Kim, Youngwoo ; Song, Seokchan ; Lee, Juhyoung ; Yoo, Hoi-Jun

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, p.37-40

IEEE

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6
A 10-bit 220-MSample/s CMOS sample-and-hold circuit
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Ata de Congresso
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A 10-bit 220-MSample/s CMOS sample-and-hold circuit

Waltari, M. ; Halonen, K.

1998 IEEE International Symposium on Circuits and Systems (ISCAS), 1998, Vol.1, p.253-256 vol.1

IEEE

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7
A 100MHz hardware-efficient boost cascaded face detection design
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Ata de Congresso
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A 100MHz hardware-efficient boost cascaded face detection design

Wei-Su Wong ; Chih-Rung Chen ; Ching-Te Chiu

2009 16th IEEE International Conference on Image Processing (ICIP), 2009, p.3237-3240

IEEE

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8
A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion
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A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion

Park, Hyunchul ; Lee, Kyeongho ; Park, Jongsun

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, p.455-458

IEEE

Sem texto completo

9
A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection
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A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection

Kawamoto, Reiya ; Taichi, Masakazu ; Kabuto, Masaya ; Watanabe, Daisuke ; Izumi, Shintaro ; Yoshimoto, Masahiko ; Kawaguchi, Hiroshi

2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, p.203-207

IEEE

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10
A 1.2 billion operations per second video signal processing chip
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A 1.2 billion operations per second video signal processing chip

Yates, R. ; Evans, S. ; Ivey, P.A.

Proceedings of 1st International Conference on Image Processing, 1994, Vol.3, p.596-600 vol.3

IEEE Comput. Soc. Press

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