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1
Stream-dataflow acceleration
Stream-dataflow acceleration
Material Type:
Acta de Congreso 		Añadir a Mi Portal

Stream-dataflow acceleration

Nowatzki, Tony ; Gangadhar, Vinay ; Ardalani, Newsha ; Sankaralingam, Karthikeyan

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.416-429

ACM

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2
DaDianNao: A Machine-Learning Supercomputer
DaDianNao: A Machine-Learning Supercomputer
Material Type:
Acta de Congreso 		Añadir a Mi Portal

DaDianNao: A Machine-Learning Supercomputer

Chen, Yunji ; Luo, Tao ; Liu, Shaoli ; Zhang, Shijin ; He, Liqiang ; Wang, Jia ; Li, Ling ; Chen, Tianshi ; Xu, Zhiwei ; Sun, Ninghui ; Temam, Olivier

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.609-622

Washington, DC, USA: IEEE Computer Society

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3
A-ViT: Adaptive Tokens for Efficient Vision Transformer
A-ViT: Adaptive Tokens for Efficient Vision Transformer
Material Type:
Acta de Congreso 		Añadir a Mi Portal

A-ViT: Adaptive Tokens for Efficient Vision Transformer

Yin, Hongxu ; Vahdat, Arash ; Alvarez, Jose M. ; Mallya, Arun ; Kautz, Jan ; Molchanov, Pavlo

2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2022, p.10799-10808

IEEE

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4
Exploring Instruction Fusion Opportunities in General Purpose Processors
Exploring Instruction Fusion Opportunities in General Purpose Processors
Material Type:
Acta de Congreso 		Añadir a Mi Portal

Exploring Instruction Fusion Opportunities in General Purpose Processors

Singh, Sawan ; Perais, Arthur ; Jimborean, Alexandra ; Ros, Alberto

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.199-212

IEEE

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5
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Material Type:
Artículo 		Añadir a Mi Portal

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Revista revisada por pares]

New York: IEEE

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6
An architecture interface and offload model for low-overhead, near-data, distributed accelerators
An architecture interface and offload model for low-overhead, near-data, distributed accelerators
Material Type:
Acta de Congreso 		Añadir a Mi Portal

An architecture interface and offload model for low-overhead, near-data, distributed accelerators

Baskaran, Saambhavi ; Kandemir, Mahmut Taylan ; Sampson, Jack

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022, p.1160-1177

IEEE

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7
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
Material Type:
Artículo 		Añadir a Mi Portal

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Revista revisada por pares]

New York: IEEE

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8
SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks
SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks
Material Type:
Acta de Congreso 		Añadir a Mi Portal

SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks

Venkataramani, Swagath ; Ranjan, Ashish ; Banerjee, Subarno ; Das, Dipankar ; Avancha, Sasikanth ; Jagannathan, Ashok ; Durg, Ajaya ; Nagaraj, Dheemanth ; Kaul, Bharat ; Dubey, Pradeep ; Raghunathan, Anand

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.13-26

ACM

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9
In-datacenter performance analysis of a tensor processing unit
In-datacenter performance analysis of a tensor processing unit
Material Type:
Acta de Congreso 		Añadir a Mi Portal

In-datacenter performance analysis of a tensor processing unit

Jouppi, Norman P. ; Borchers, Al ; Boyle, Rick ; Cantin, Pierre-luc ; Chao, Clifford ; Clark, Chris ; Coriell, Jeremy ; Daley, Mike ; Dau, Matt ; Dean, Jeffrey ; Gelb, Ben ; Young, Cliff ; Ghaemmaghami, Tara Vazir ; Gottipati, Rajendra ; Gulland, William ; Hagmann, Robert ; Ho, C. Richard ; Hogberg, Doug ; Hu, John ; Hundt, Robert ; Hurt, Dan ; Ibarz, Julian ; Patil, Nishant ; Jaffey, Aaron ; Jaworski, Alek ; Kaplan, Alexander ; Khaitan, Harshit ; Killebrew, Daniel ; Koch, Andy ; Kumar, Naveen ; Lacy, Steve ; Laudon, James ; Law, James ; Patterson, David ; Le, Diemthu ; Leary, Chris ; Liu, Zhuyuan ; Lucke, Kyle ; Lundin, Alan ; MacKean, Gordon ; Maggiore, Adriana ; Mahony, Maire ; Miller, Kieran ; Nagarajan, Rahul ; Agrawal, Gaurav ; Narayanaswami, Ravi ; Ni, Ray ; Nix, Kathy ; Norrie, Thomas ; Omernick, Mark ; Penukonda, Narayana ; Phelps, Andy ; Ross, Jonathan ; Ross, Matt ; Salek, Amir ; Bajwa, Raminder ; Samadiani, Emad ; Severn, Chris ; Sizikov, Gregory ; Snelham, Matthew ; Souter, Jed ; Steinberg, Dan ; Swing, Andy ; Tan, Mercedes ; Thorson, Gregory ; Tian, Bo ; Bates, Sarah ; Toma, Horia ; Tuttle, Erick ; Vasudevan, Vijay ; Walter, Richard ; Wang, Walter ; Wilcox, Eric ; Yoon, Doe Hyun ; Bhatia, Suresh ; Boden, Nan

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.1-12

ACM

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10
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
Material Type:
Artículo 		Añadir a Mi Portal

Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Sun, Hanbo ; Zhu, Zhenhua ; Wang, Chenyu ; Ning, Xuefei ; Dai, Guohao ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Revista revisada por pares]

New York: IEEE

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