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1 |
Material Type: Artigo
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Direct Current Generation in Single-Phase Residential Systems DC Effects and Permissible LevelsEmanuel, A. E. ; Pileggi, D. J. ; Levitsky, F. J.IEEE transactions on power apparatus and systems, 1984-08, Vol.PAS-103 (8), p.2051-2057New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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The use of simulation in semiconductor technology developmentCole, D.C. ; Buturla, E.M. ; Furkay, S.S. ; Varahramyan, K. ; Slinkman, J. ; Mandelman, J.A. ; Foty, D.P. ; Bula, O. ; Strong, A.W. ; Park, J.W. ; Linton, T.D. ; Johnson, J.B. ; Fischetti, M.V. ; Laux, S.E. ; Cottrell, P.E. ; Lustig, H.G. ; Pileggi, F. ; Katcoff, D.Solid-state electronics, 1990-06, Vol.33 (6), p.591-623 [Periódico revisado por pares]Elsevier LtdTexto completo disponível |
3 |
Material Type: Artigo
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Incessant Ectopic Atrial Tachycardia and Sudden DeathSOSA, EDUARDO ; MARCIAL, MIGUEL BARBERO ; SCANAVACCA, MAURICIO ; BELLOTTI, GIOVANNI ; PILEGGI, FULVIOPacing and clinical electrophysiology, 1991-05, Vol.14 (5), p.764-767 [Periódico revisado por pares]Oxford, UK: Blackwell Publishing LtdTexto completo disponível |
4 |
Material Type: Artigo
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A comparison of the electrochromic behavior and the mechanical properties of WO3 and NiOx thin film electrodesDECKER, F ; PILEGGI, R ; PASSERINI, S ; SCROSATI, BJournal of the Electrochemical Society, 1991-11, Vol.138 (11), p.3182-3186 [Periódico revisado por pares]Pennington, NJ: Electrochemical SocietyTexto completo disponível |
5 |
Material Type: Ata de Congresso
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RC-interconnect macromodels for timing simulationDartu, F. ; Tutuianu, B. ; Pileggi, L.T.33rd Design Automation Conference Proceedings, 1996, 1996, p.544-547IEEETexto completo disponível |
6 |
Material Type: Ata de Congresso
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An explicit RC-circuit delay approximation based on the first three moments of the impulse responseTutuianu, B. ; Dartu, F. ; Pileggi, L.33rd Design Automation Conference Proceedings, 1996, 1996, p.611-616IEEETexto completo disponível |
7 |
Material Type: Artigo
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Performance computation for precharacterized CMOS gates with RC loadsDartu, F. ; Menezes, N. ; Pileggi, L.T.IEEE transactions on computer-aided design of integrated circuits and systems, 1996-05, Vol.15 (5), p.544-553 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
8 |
Material Type: Ata de Congresso
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Clustering and load balancing for buffered clock tree synthesisMehta, A.D. ; Yao-Ping Chen ; Menezes, N. ; Wong, D.F. ; Pilegg, L.T.Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.217-223IEEETexto completo disponível |
9 |
Material Type: Ata de Congresso
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CMOS gate delay models for general RLC loadingArunachalam, R. ; Dartu, F. ; Pileggi, L.T.Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.224-229IEEETexto completo disponível |
10 |
Material Type: Ata de Congresso
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Calculating worst-case gate delays due to dominant capacitance couplingDartu, Florentin ; Pileggi, Lawrence T.Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.46-51New York, NY, USA: ACMTexto completo disponível |