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A 65 nm Cryptographic Processor for High Speed Pairing Computation
A 65 nm Cryptographic Processor for High Speed Pairing Computation
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A 65 nm Cryptographic Processor for High Speed Pairing Computation

Jun Han ; Yang Li ; Zhiyi Yu ; Xiaoyang Zeng

IEEE transactions on very large scale integration (VLSI) systems, 2015-04, Vol.23 (4), p.692-701 [Periódico revisado por pares]

IEEE

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12
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
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A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration

Niitsu, K. ; Kawai, S. ; Miura, N. ; Ishikuro, H. ; Kuroda, T.

IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1285-1294 [Periódico revisado por pares]

New York, NY: IEEE

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13
A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology
A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology
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A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology

Wu, Yue-Ming ; Kao, Yu-Hsien ; Chu, Ta-Shun

IEEE transactions on very large scale integration (VLSI) systems, 2022-01, Vol.30 (1), p.29-39 [Periódico revisado por pares]

New York: IEEE

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14
ABRM: Adaptive \beta-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling
ABRM: Adaptive \beta-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling
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ABRM: Adaptive \beta-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Myeong-Eun Hwang ; Roy, K.

IEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.281-290 [Periódico revisado por pares]

New York, NY: IEEE

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15
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach
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Accelerating Recurrent Neural Networks: A Memory-Efficient Approach

Wang, Zhisheng ; Lin, Jun ; Wang, Zhongfeng

IEEE transactions on very large scale integration (VLSI) systems, 2017-10, Vol.25 (10), p.2763-2775 [Periódico revisado por pares]

IEEE

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16
Achieving Programming Model Abstractions for Reconfigurable Computing
Achieving Programming Model Abstractions for Reconfigurable Computing
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Achieving Programming Model Abstractions for Reconfigurable Computing

Andrews, D. ; Sass, R. ; Anderson, E. ; Agron, J. ; Peck, W. ; Stevens, J. ; Baijot, F. ; Komp, E.

IEEE transactions on very large scale integration (VLSI) systems, 2008-01, Vol.16 (1), p.34-44 [Periódico revisado por pares]

New York: IEEE

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17
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
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Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving

Masuda, Yutaka ; Onoye, Takao ; Hashimoto, Masanori

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2217-2229 [Periódico revisado por pares]

New York: IEEE

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18
Active Cache Emulator
Active Cache Emulator
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Active Cache Emulator

Nurvitadhi, E. ; Jumnit Hong ; Shih-Lien Lu

IEEE transactions on very large scale integration (VLSI) systems, 2008-03, Vol.16 (3), p.229-240 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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19
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip
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Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip

Samman, Faizal Arya ; Hollstein, Thomas ; Glesner, Manfred

IEEE transactions on very large scale integration (VLSI) systems, 2010-07, Vol.18 (7), p.1067-1080 [Periódico revisado por pares]

New York: IEEE

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20
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
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Adaptive Cooling of Integrated Circuits Using Digital Microfluidics

Paik, P.Y. ; Pamula, V.K. ; Chakrabarty, K.

IEEE transactions on very large scale integration (VLSI) systems, 2008-04, Vol.16 (4), p.432-443 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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