skip to main content
Idioma:
Refinado por: Base de dados/Biblioteca: ANTE: Abstracts in New Technology & Engineering remover Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover
Result Number Material Type Add to My Shelf Action Record Details and Options
1
Three-dimensional place and route for FPGAs
Three-dimensional place and route for FPGAs
Material Type:
Artigo 		Adicionar ao Meu Espaço

Three-dimensional place and route for FPGAs

Ababei, C. ; Mogal, H. ; Bazargan, K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1132-1140 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
2
Parameterized Non-Gaussian Variational Gate Timing Analysis
Parameterized Non-Gaussian Variational Gate Timing Analysis
Material Type:
Artigo 		Adicionar ao Meu Espaço

Parameterized Non-Gaussian Variational Gate Timing Analysis

Abbaspour, S.. ; Fatemi, H.. ; Pedram, M..

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-08, Vol.26 (8), p.1495-1508 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
3
A boundary gradient search technique and its applications in design centering
A boundary gradient search technique and its applications in design centering
Material Type:
Artigo 		Adicionar ao Meu Espaço

A boundary gradient search technique and its applications in design centering

Abdel-Malek, H.L. ; Hassan, A.-K.S.O. ; Heaba, M.H.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-11, Vol.18 (11), p.1654-1660 [Periódico revisado por pares]

IEEE

Texto completo disponível

Citações Citado por
4
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
Material Type:
Artigo 		Adicionar ao Meu Espaço

Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits

Abderrahman, A. ; Cerny, E. ; Kaminska, B.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-03, Vol.18 (3), p.332-345 [Periódico revisado por pares]

New York, NY: IEEE

Texto completo disponível

Citações Citado por
5
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions
Material Type:
Artigo 		Adicionar ao Meu Espaço

Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions

Abdollahi, A. ; Pedram, M.

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-06, Vol.27 (6), p.1128-1137 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
6
Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST
Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST
Material Type:
Artigo 		Adicionar ao Meu Espaço

Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST

Abu-Issa, A.S. ; Quigley, S.F.

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-05, Vol.28 (5), p.755-759 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
7
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
Material Type:
Artigo 		Adicionar ao Meu Espaço

A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations

Abu-Rahma, M.H. ; Anis, M.

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-11, Vol.27 (11), p.1983-1995 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
8
TETA: transistor-level waveform evaluation for timing analysis
TETA: transistor-level waveform evaluation for timing analysis
Material Type:
Artigo 		Adicionar ao Meu Espaço

TETA: transistor-level waveform evaluation for timing analysis

Acar, E. ; Dartu, F. ; Pileggi, L.T.

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-05, Vol.21 (5), p.605-616 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
9
Low-Cost Characterization and Calibration of RF Integrated Circuits through I- Q Data Analysis
Low-Cost Characterization and Calibration of RF Integrated Circuits through I- Q Data Analysis
Material Type:
Artigo 		Adicionar ao Meu Espaço

Low-Cost Characterization and Calibration of RF Integrated Circuits through I- Q Data Analysis

Acar, E. ; Ozev, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-07, Vol.28 (7), p.993-1005 [Periódico revisado por pares]

IEEE

Texto completo disponível

Citações Citado por
10
Defect-Oriented Testing of RF Circuits
Defect-Oriented Testing of RF Circuits
Material Type:
Artigo 		Adicionar ao Meu Espaço

Defect-Oriented Testing of RF Circuits

Acar, E. ; Ozev, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-05, Vol.27 (5), p.920-931 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por

Personalize Seus Resultados

  1. Editar

Refine Search Results

Expandir Meus Resultados

  1.   

Data de Publicação 

De até
Refinar
  1. Antes de2001  (273)
  2. 2001Até2003  (386)
  3. 2004Até2007  (541)
  4. 2008Até2011  (664)
  5. Após 2011  (443)
  6. Mais opções open sub menu

  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

Buscando em bases de dados remotas. Favor aguardar.