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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover assunto: Science & Technology remover
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DefScan: Provably Defeating Scan Attack on AES-Like Ciphers
DefScan: Provably Defeating Scan Attack on AES-Like Ciphers
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DefScan: Provably Defeating Scan Attack on AES-Like Ciphers

Sao, Yogendra ; Ali, Sk. Subidh ; Mazumdar, Bodhisatwa

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2326-2339 [Periódico revisado por pares]

New York: IEEE

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2
ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach
ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach
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ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach

Shi, Zhanhui ; Xiao, Jie ; Jiang, Jianhui ; Zhang, Ying ; Zhou, Yuhao

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2479-2492 [Periódico revisado por pares]

New York: IEEE

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3
Tamper Resistant Reconfigurable Preamplifier Physical Unclonable Function With Self-Destruct
Tamper Resistant Reconfigurable Preamplifier Physical Unclonable Function With Self-Destruct
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Tamper Resistant Reconfigurable Preamplifier Physical Unclonable Function With Self-Destruct

Hunt-Schroeder, Eric ; Xia, Tian

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2301-2311 [Periódico revisado por pares]

New York: IEEE

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4
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology
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Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology

Liu, Lixin ; Liu, Tianji ; Jiang, Bentian ; Young, Evangeline F. Y.

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2426-2439 [Periódico revisado por pares]

New York: IEEE

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5
Accelerating Real-Valued FFT on CPU-FPGA Platforms
Accelerating Real-Valued FFT on CPU-FPGA Platforms
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Accelerating Real-Valued FFT on CPU-FPGA Platforms

Qian, Zhuo ; Gan, Guoyou

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2532-2536 [Periódico revisado por pares]

New York: IEEE

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6
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
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Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment

Sarkar, Ardhendu ; Ghosh, Surajeet

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2365-2378 [Periódico revisado por pares]

New York: IEEE

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7
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults
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GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults

Shin, Seung Ho ; Lee, Hayoung ; Kang, Sungho

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2518-2531 [Periódico revisado por pares]

New York: IEEE

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8
Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks
Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks
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Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks

Chen, Ching-Yuan ; Joardar, Biresh Kumar ; Doppa, Janardhan Rao ; Pande, Partha Pratim ; Chakrabarty, Krishnendu

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2411-2425 [Periódico revisado por pares]

New York: IEEE

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9
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints
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Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints

Dekimpe, Remi ; Bol, David

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2507-2517 [Periódico revisado por pares]

New York: IEEE

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10
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints
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3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints

Pandey, Shailja ; Sethi, Sayam ; Panda, Preeti Ranjan

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2263-2276 [Periódico revisado por pares]

New York: IEEE

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